MAX7358 Maxim, MAX7358 Datasheet - Page 17

• Manufacturer Part Number: MAX7358
• Description: The MAX7356/MAX7357/MAX7358 8-channel I²C switches/multiplexers expand the main I²C bus to any combination of 8 extended I²C buses
• Manufacturer: Maxim

2 seconds. The interrupt signal asserts again once a
new lock-up is detected. The interrupt signal does not
activate the reset function.
The MAX7356/MAX7357/MAX7358 operate as a slave
that sends and receives data through an I
Figure 10. Bus Lock-Up During a 3-Byte Write Command
Figure 11. Start and Stop Conditions
Figure 12. Bit Transfer
Figure 13. Acknowledge
SDA
SCL
SDA
SCL
CONDITION
CONDITION
SDA
SCL
START
1-to-8 I
Lock-Up Detection, Isolation, and Notification
START
S
S
START
DATA STABLE
DATA VALID
0
1
1
______________________________________________________________________________________
1
2
2
DATA ALLOWED
C Bus Switches/Multiplexers with Bus
0
CHANGE OF
THE TROUBLED DEVICE
ACKNOWLEDGE FROM
1
NOT ACKNOWLEDGE
0
ACKNOWLEDGE
0
ACKNOWLEDGMENT
CLOCK PULSE FOR
W
Serial Interface
8
Serial Addressing
0
A
2
9
C interface.
0
CONDITION
1
STOP
P
LOCK-UP
OCCURS
1
FIRST DATA BYTE
0
L
The interface uses a serial-data line (SDA) and a serial-
clock line (SCL) to achieve bidirectional communication
between master(s) and slave(s). The master initiates all
data transfers to and from the MAX7357 or MAX7358
and generates the SCL clock that synchronizes the
data transfer.
SDA operates as both an input and an open-drain out-
put. A pullup resistor (4.7kΩ, typ) is required on SDA.
SCL operates only as an input. A pullup resistor (4.7kΩ,
typ) is required on SCL if there are multiple masters on
the 2-wire interface, or if the master in a single-master
system has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the MAX7356/MAX7357/
MAX7358’s 7-bit slave address plus R/W bit, and then
optionally 1 or more data bytes, and finally a STOP con-
dition (Figure 10).
Both SCL and SDA remain high when the interface is
not busy. The master signals the beginning of a trans-
mission with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 11).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 12).
The acknowledge bit is a clocked 9th bit the recipient
uses to handshake receipt of each byte of data (Figure
13). Each byte transferred effectively requires 9 bits.
The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line is stable low during the
high period of the clock pulse. When the master is
transmitting to the MAX7356/MAX7357/MAX7358, the
MAX7356/MAX7357/MAX7358 generate the acknowl-
L
L
L
L
L
L
START and STOP Conditions
SECOND DATA BYTE
L
L
L
L
L
L
Acknowledge
Bit Transfer
L
L
17