ADV7162KS220 Analog Devices Inc, ADV7162KS220 Datasheet - Page 30

• Manufacturer Part Number: ADV7162KS220
• Description: IC DAC VIDEO COLOR 96BIT 160MQFP
• Manufacturer: Analog Devices Inc
• Type: Video DACr

Specifications of ADV7162KS220

• Rohs Status: RoHS non-compliant
• Applications: HDTV
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP

ADV7160/ADV7162
Signature Reset Control (CR46)
Taking CR46 low then high resets the signature analyzer. This is
done to give a known starting point before acquiring a signature.
Signature Acquire Control (CR47)
This bit should be set to Logic “1” for normal operation. See
“Test Diagnostic” section for more information.
COMMAND REGISTER 5 (CR5)
(Address Reg (A10–A0) = 00DH)
This register contains one control bit CR56. CR5 is a 10-bit
wide register. However for programming purposes, it may be
considered as an 8-bit wide register (CR59 and CR58 are both
reserved).
This register can be read from as well written to. Control Bit
CR56 selects either external clock or internal PLL operation. If
the internal PLL is to be used, Logic “1” should be written to
CR56.This should be set up immediately after power up. In
write mode, zero should be written to CR57 and CR55–CR50.
In read mode, CR59 and CR58 are both returned as zeros.
PLL COMMAND REGISTER (PCR)
(Address Reg (A10–A0) = 009H)
This register contains a number of control bits as shown in the
diagram. PCR is a 10-bit wide register. However, for program-
ming purposes, it may be considered as an 8-bit wide register
(PCR9 and PCR8 are both reserved).
Figure 44 shows the various operations under the control of
PCR. This register can be read from as well written to. In write
mode zero should be written to PCR3. In read mode PCR9 and
PCR8 are returned as zeros.
PLL Control (PCR0)
This bit enables or disables PLL.
RSEL Bit Control (PCR1)
This bit enables or disables RSEL, which together with the con-
tents of the PLL R Register affect the reference divider value of
the PLL. Reference Divider = (1 + RSEL) (R+2).
VSEL Bit Control (PCR2)
This bit enables or disables VSEL, which together with the
contents of the PLL V Register and the PLL S value affect the
feedback divider value of the PLL.
Feedback Divider = (1 + VSEL)
*
THESE BITS ARE READ-ONLY
RESERVED BITS.
A READ CYCLE WILL RETURN
ZEROS "00."
PCR9
RESERVED*
PCR8
(4(V + 2)+S).
Figure 44. Command Register (PCR) (PCR9–PCR0)
PCR7 PCR6
(S1
PCR7
0
0
1
1
S VALUE
S0)
0
1
0
1
PCR6
(PSEL1 PSEL0)
PCR5 PCR4
0
1
2
3
0
0
1
1
F
0
1
0
1
OUT
PCR5
–30–
VCO/1
VCO/2
VCO/4
VCO/8
Output Divide Control (PCR5–PCR4)
These bits control the PLL output divider. This post-scaler
is used in the generation of lower frequencies.
PLL S Control (PCR7–PCR6)
These bits set up the S value in the PLL transfer function.
This extra value provides extra control in setting the feed-
back divider value of the PLL.
Status Register
(Address Reg (A10–A0) = 00AH)
This register is a read only 10-bit register. However SR9–
SR8 are reserved bits, containing zeros and SR7–SR1 are
undefined bits and should be masked in software on read
back. Therefore, SR0 is the only relevant Bit in the Status
Register and contains a Logic “1” if one, or more of the
IOR, IOG, and IOB outputs exceed the internal voltage of
the SENSE comparator circuit . It can be used to deter-
mine the presence of a CRT monitor. With some diagnos-
tic code, the presence of loading on the individual RGB
lines can be determined. The reference is generated by a
voltage divider from the external voltage reference on the
V
should be applied to the comparator by the IOR, IOG and
IOB outputs:
Revision Register
(Address Reg (A10–A0) = 01BH)
This register is a read only register containing the revision
of silicon.
PLL R Register
(Address Reg (A10–A0) = 00CH)
This register is a read only 10-bit register. However, R9–R8
are reserved bits, containing zeros. Bit R7 is a read only bit.
This bit should be masked in software on readback as its
value may be indeterminate. Therefore, the PLL R Register
may be treated as a 7-bit wide register. This register, to-
gether with the RSEL Bit in the PLL Control Register, con-
trols the reference divider of the on-board PLL.
RE F
PCR4
DAC Low Voltage
DAC High Voltage
BE WRITTEN TO
ZERO SHOULD
pin. For the proper operation, the following levels
THIS BIT
PCR2
PCR5
0
1
(0)
VSEL ENABLE
PCR3
DISABLE
ENABLE
PCR2
PCR1
250 mV
0
1
450 mV
RSEL ENABLE
PCR0
DISABLE
ENABLE
0
1
PCR1
PLL CONTROL
DISABLE PLL
ENABLE PLL
PCR0
REV. 0