AD9889KSTZ-80 Analog Devices Inc, AD9889KSTZ-80 Datasheet - Page 40

• Manufacturer Part Number: AD9889KSTZ-80
• Description: TRANSMITTER HDMI/DVI 80-LQFP
• Manufacturer: Analog Devices Inc
• Type: HDMI, DVI Transmitterr

Specifications of AD9889KSTZ-80

• Applications: Recorders, Set-Top Boxes
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9889
2-WIRE SERIAL CONTROL PORT
A 2-wire serial interface is provided. Up to two AD9889 devices
can be connected to the 2-wire serial interface, with each device
having a unique address.
The 2-wire serial interface comprises a clock (SCL) and a
bidirectional data (SDA) pin. The analog flat panel interface
acts as a slave for receiving and transmitting data over the serial
interface. When the serial interface is not active, the logic levels
on SCL and SDA are pulled high by external pull-up resistors.
Data received or transmitted on the SDA line must be stable for
the duration of the positive going SCL pulse. Data on SDA must
change only when SCL is low. If SDA changes state while SCL is
high, the serial interface interprets that action as a start or stop
sequence.
There are five components to serial bus operation:
•
•
•
•
•
When the serial interface is inactive (SCL and SDA are high)
communications are initiated by sending a start signal. The start
signal is a high-to-low transition on SDA while SCL is high.
This signal alerts all slave devices that a data transfer sequence
is coming.
The first 8 bits of data transferred after a start signal comprise a
7-bit slave address (the first 7 bits) and a single R/ W bit (the
eighth bit). The R/ W bit indicates the direction of data transfer,
read from (1) or write to (0) the slave device. If the transmitted
slave address matches the address of the device, the AD9889
acknowledges by bringing SDA low on the ninth SCL pulse. If
the addresses do not match, the AD9889 does not acknowledge.
Table 29. Serial Port Addresses
Bit 7
A
0
0
6
(MSB)
Start signal
Slave address byte
Base register address byte
Data byte to read or write
Stop signal
Bit 6
A
1
1
5
SDA
SCL
t
Bit 5
A
1
1
t
STAH
BUFF
4
Bit 4
A
1
1
3
t
DHO
Bit 3
A
0
0
2
t
DAL
Bit 2
A
0
0
1
Figure 11. Serial Port Read/Write Timing
t
DAH
t
Bit 1
A
0
1
DSU
0
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DATA TRANSFER VIA SERIAL INTERFACE
For each byte of data read or written, the MSB is the first bit of
the sequence.
If the AD9889 does not acknowledge the master device during
a write sequence, the SDA remains high so the master can
generate a stop signal. If the master device does not acknowl-
edge the AD9889 during a read sequence, the AD9889 inter-
prets this as the end of data. The SDA remains high so the
master can generate a stop signal.
Writing data to specific control registers of the AD9889 re-
quires that the 8-bit address of the control register of interest
be written to after the slave address has been established. This
control register address is the base address for subsequent write
operations. The base address auto-increments by one for each
byte of data written after the data byte intended for the base
address.
Data is read from the control registers of the AD9889 in a
similar manner. Reading requires two data transfer operations:
•
•
To terminate a read/write sequence to the AD9889, a stop signal
must be sent. A stop signal comprises a low-to-high transition
of SDA while SCL is high.
A repeated start signal occurs when the master device driving the
serial interface generates a start signal without first generating a
stop signal to terminate the current communication. This is used to
change the mode of communication (read, write) between the slave
and master without releasing the serial interface lines.
The base address must be written with the R/ W bit of the
slave address byte low to set up a sequential read operation.
Reading (the R/ W bit of the slave address byte high) begins
at the previously established base address. The address of
the read register auto-increments after each byte is
transferred.
t
STASU
t
STOSU