MAX9403 Maxim, MAX9403 Datasheet - Page 3

• Manufacturer Part Number: MAX9403
• Description: The MAX9400/MAX9402/MAX9403/MAX9405 are extremely fast, low-skew quad LVECL/ECL or LVPECL/PECL buffer/receivers designed for high-speed data and clock driver applications
• Manufacturer: Maxim

AC ELECTRICAL CHARACTERISTICS
(V
time = 125ps (20% to 80%), V
unless otherwise noted. Typical values are at V
noted.) (Notes 1, 4)
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full oper-
Note 4: Guaranteed by design and characterization. Limits are set to ±6 sigma.
Note 5: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 6: Device jitter added to the input signal.
IN-to-OUT Differential
Propagation Delay
CLK-to-OUT Differential
Propagation Delay
IN-to-OUT Channel-to-Channel
Skew (Note 5)
CLK-to-OUT Channel-to-
Channel Skew (Note 5)
Maximum Clock Frequency
Maximum Data Frequency
Added Random Jitter (Note 6)
Added Deterministic Jitter
(Note 6)
IN-to-CLK Setup Time
CLK-to-IN Hold Time
Output Rise Time
Output Fall Time
Propagation Delay Temperature
Coefficient
CC
- V
EE
ating temperature range.
PARAMETER
= 2.375V to 5.5V, outputs terminated with 50Ω ±1% to V
_______________________________________________________________________________________
IHD
= V
f
SYMBOL
CLK(MAX)
f
EE
IN(MAX)
t
t
t
t
t
t
∆t
SKD1
SKD2
PLH1
PHL1
PLH2
PHL2
t
t
∆T
t
DJ
t
t
t
+ 1.2V to V
RJ
PD
H
S
R
F
Quad Differential LVECL/LVPECL
/
CC
MAX9400/MAX9403
MAX9402/MAX9405
MAX9400/MAX9403
MAX9402/MAX9405
SEL = high
SEL = low
V
V
SEL = low, f
SEL = high, f
SEL = low, f
2
SEL = high, IN = 2.0Gbps 2
pattern
Figure 4
Figure 4
Figure 3
Figure 3
23
OH
OH
- V
CC
- 1 PRBS pattern
- V
- V
EE
, V
OL
OL
= 3.3V, V
ILD
≥ 500mV, SEL = low
≥ 400mV, SEL = high
CLK
CLK
= V
IN
CONDITIONS
= 2GHz
EE
= 3.0GHz clock, f
= 3.0GHz, IN_ = 3.0Gbps
IHD
CC
to V
= V
- 2.0V, enabled, CLK = 3.2GHz, f
CC
SEL = high, Figure 3
SEL = low, Figure 4
CC
- 0.2V, V
23
- 0.9V, V
- 1 PRBS
IN
IHD
= 1.5GHz
ILD
Buffer/Receivers
- V
= V
ILD
CC
= 0.2V to smaller of |V
1.7V, T
MIN
237
237
397
397
3.0
80
80
2
A
IN
= +25°C, unless otherwise
= 1.6GHz, input transition
TYP
0.64
0.74
335
335
475
475
0.2
16
17
40
80
80
8
MAX
CC
437
437
597
597
120
120
1.3
1.5
80
55
30
55
1
- V
EE
ps
UNITS
ps
ps/°C
| or 3V,
GHz
GHZ
(RMS)
ps
ps
ps
ps
ps
ps
ps
ps
(P-P)
3