IR3500VMPBF International Rectifier, IR3500VMPBF Datasheet - Page 26

• Manufacturer Part Number: IR3500VMPBF
• Description: The IR3500V Control IC combined with one or more xPhase3 Phase IC implement the control and MOSFET driver functions for a VR11.1 CPU VTT power supply.
• Manufacturer: International Rectifier

Specifications of IR3500VMPBF

• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 250kHz to 1.5MHz
• Pbf: PbF Option Available

Where; I
No Load Output Voltage Setting Resistor R
A resistor between VSETPT pin and VDAC is used to create output voltage offset V
difference between V
I
VCCL Capacitor C
driven. The linear regulator supplies the bias and gate drive current of the phase ICs. A 4.7uF normally ensures
stable VCCL performance.
VCCL Programming Resistor R
Since VCCL voltage is proportional to the MOSFET gate driver loss and inversely proportional to the
MOSFET conduction loss, the optimum voltage should be chosen to maximize the converter efficiency. VCCL
linear regulator consists of an external NPN transistor, a ceramic capacitor and a programmable resistor
divider. Pre-select R
VCCL Regulator Drive Resistor R
minimum input voltage requirements. The following equation gives an estimate of the average load current of
the switching phase ICs.
Q
VCCL, the maximum R
Due to limited pull down capability of the VCCLDRV pin, make sure the following condition is satisfied.
VSETPT
The capacitor is selected based on the stability requirement of the linear regulator and the load current to be
The drive resistor is primarily dependent on the load current requirement of the linear regulator and the
gb
and Q
G
D=Vo/V
is the current flowing out of VSETPT pin as shown in Figure 23.
Page 26 of 34
LIMIT
CS
gt
=Over current limit, n=Number of phases, K
=Gain of the current sense amplifier, I
are the gate charge of the top and bottom FET. For a minimum input voltage and a maximum
I
, m=Maximum integer that doesn’t exceed (n*D)
VCCL
VCCLFB1
DAC
VCCLDRV
K
R
I
voltage and output voltage at no load condition. R
drive
OCSET
P
=
R
, and calculate R
_
R
VCCLDRV



avg
VCCLFB
V
required to use the full pull-down current of the VCCL driver is given by
I
=
⋅
VCCLFB1
=
[
D
(
I
I
[
LIMIT
LIMIT
VCCLDRV
⋅
(
2
1 (
n
Q
=
=
−
V
gb
/
D
R
I
n
∗
VCCL
+
(min)
VCCLFB
)
)
R
⋅
and R
⋅
Q
L
R
L
n
VSETPT
_
⋅
gt
⋅
I
VCCLFB2
(
MAX
f
drive
VSETPT
)
D
−
sw
−
1
⋅
*
. 1
0
−
⋅
VCCLFB2
f
_
. 1
2
7 .
∗
OCSET
19
sw
avg
m
n
⋅
=
19
1 (
−
D
)
+
V
⋅
VCCL
/
+
,
⋅
(
10
O
β
1 (
from (15).
I
m
K
= Determined by the ROSC and given by Figure 10,
VSETPT
P
_
min
n
−
=Ratio of the peak to average current for the inductor,
mA
P
+
NLOFST
)
D
1
(max)
+
)
−
]
V
⋅
D
CS
n
)



_
TOFST
]
∗
G
CS
/
VSETPT
I
(15)
OCSET
(17)
(16)
is determined by (14), where
(13)
(12)
O_NLOFST,
(14)
July 28, 2008
IR3500V
which is the