IR3553MTRPBF International Rectifier, IR3553MTRPBF Datasheet

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IR3553MTRPBF

Manufacturer Part Number
IR3553MTRPBF
Description
The IR3553 integrated PowIRstage is a synchronous buck gate driver IC with co‐packed control and synchronous MOSFETs and Schottky diode.
Manufacturer
International Rectifier
Datasheet

Specifications of IR3553MTRPBF

Package
PQFN / 4 x 6
Iout (a)
40
Switch Freq (khz)
up to 1.0MHz
Input Range (v)
4.5 - 15
Output Range (v)
0.25 - (VCC -2.5)

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FEATURES
APPLICATIONS
BASIC APPLICATION
PHSFLT#
4.5V to 7V
BBRK#
PWM
REFIN
VCC
IOUT
 Peak efficiency up to 93.2% at 1.2V
 Integrated driver, control MOSFET, synchronous
 Input voltage (VIN) operating range up to 15V
 Output voltage range from 0.25V up to 3.3V
 Output current capability of 40A DC
 Operation up to 1.0MHz
 Integrated current sense amplifier
 VCC under voltage lockout
 Thermal flag
 Body-Braking® load transient support
 Diode-emulation high efficiency mode
 Compatible with 3.3V PWM logic and VCC tolerant
 Compliant with Intel DrMOS V4.0
 PCB footprint compatible with IR3550 and IR3551
 Efficient dual sided cooling
 Small 4mm x 6mm x 0.9mm PQFN package
 Lead free RoHS compliant package
 Voltage Regulators for CPUs, GPUs, and DDR
 High current, low profile DC-DC converters
MOSFET and Schottky diode
memory arrays
Figure 1: IR3553 Basic Application Circuit
1
VCC
PHSFLT#
PWM
REFIN
BBRK#
IOUT
LGND
March 12, 2012 | FINAL DATASHEET
IR3553
BOOST
CSIN+
PGND
CSIN-
VIN
SW
4.5V to 15V
40A Integrated PowIRstage®
VOUT
VIN
DESCRIPTION
The IR3553 integrated PowIRstage® is a synchronous buck
gate driver co-packed with a control MOSFET and a
synchronous MOSFET with integrated Schottky diode. It is
optimized internally for PCB layout, heat transfer and
driver/MOSFET timing. Custom designed gate driver and
MOSFET combination enables higher efficiency at lower
output voltages required by cutting edge CPU, GPU and
DDR memory designs.
Up to 1.0MHz switching frequency enables high
performance transient response, allowing miniaturization
of output inductors, as well as input and output capacitors
while maintaining industry leading efficiency. The IR3553’s
superior efficiency enables smallest size and lower solution
cost. The IR3553 PCB footprint is compatible with the
IR3550 (60A) and the IR3551 (50A).
Integrated current sense amplifier achieves superior
current sense accuracy and signal to noise ratio vs. best-in-
class controller based Inductor DCR sense methods.
The IR3553 incorporates the Body- Braking® feature which
enables reduction of output capacitors. Synchronous diode
emulation mode in the IR3553 removes the zero-current
detection burden from the PWM controller and increases
system light-load efficiency.
The IR3553 is optimized specifically for CPU core power
delivery in server applications. The ability to meet the
stringent requirements of the server market also makes
the IR3553 ideally suited to powering GPU and DDR
memory designs and other high current applications.
Figure 2: Typical IR3553 Efficiency & Power Loss
94
92
90
88
86
84
82
80
78
76
74
0
5
10
15
Output Current (A)
20
25
IR3553
30
(See Note 2 on Page 8)
35
40
20
18
16
14
12
10
8
6
4
2
0

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IR3553MTRPBF Summary of contents

Page 1

FEATURES  Peak efficiency up to 93.2% at 1.2V  Integrated driver, control MOSFET, synchronous MOSFET and Schottky diode  Input voltage (VIN) operating range up to 15V  Output voltage range from 0.25V up to 3.3V  Output current ...

Page 2

... VCC VIN BOOST Gate SW Drivers and Current Sense Amplifier PGND PGND 4 CSIN- CSIN IR3553 Tape & Reel Qty Part Number 3000 IR3553MTRPBF Qty Part Number 100 IR3553MPBF VIN 4.5V to 15V C1 C2 0.1uF 10uF 0.22uF 150nH C6 C7 22uF 470uF 6- ...

Page 3

TYPICAL APPLICATION DIAGRAM (CONTINUED) VCC C3 4. 0.1uF R1 IR3553 10k 18 PHSFLT# PHSFLT# 19 PWM PWM 20 BBRK# BBRK# 21 LGND 22 REFIN 23 IOUT TGND 24 No Connect Figure 5: Application Circuit without Current Sense Amplifier ...

Page 4

PIN DESCRIPTIONS PIN # PIN NAME 1 CSIN- 2 CSIN+ 3 VCC 4, 12, 13 PGND 5, 25 GATEL 6 – – 16 VIN 17 BOOST 18 PHSFLT# 19 PWM 20 BBRK# 21 LGND 22 REFIN 23 ...

Page 5

... MSL Rating Reflow Temperature Note: 1. Thermal Resistance (θ measured with the component mounted on a high effective thermal conductivity test board in free air. JA Refer to International Rectifier Application Note AN-994 for details. March 12, 2012 | FINAL DATASHEET 5 40A Integrated PowIRstage® MAX MIN VCC + 0 ...

Page 6

ELECTRICAL SPECIFICATIONS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. Typical values represent the median values, which are related to 25°C. RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN PARAMETER Recommended VIN Range Recommended ...

Page 7

PARAMETER Slew Rate Differential Input Range Common Mode Input Range Output Impedance (IOUT) IOUT Sink Current Diode Emulation Mode Comparator Input Offset Voltage Leading Edge Blanking Time Negative Current Time-Out Digital Input – BBRK# Input voltage high Input voltage low ...

Page 8

PARAMETER VCC Supply Current VIN Supply Leakage Current BOOST Supply Current REFIN Bias Current SW Floating Voltage SW Pull Down Resistance Notes 1. Guaranteed by design but not tested in production 2. V =12V, V =1.2V, ƒ = 300kHz, L=210nH ...

Page 9

TYPICAL OPERATING CHARACTERISTICS Circuit of Figure 32, V =12V, V =1.2V, ƒ IN OUT 8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise ...

Page 10

TYPICAL OPERATING CHARACTERISTICS (CONTINUED) Circuit of Figure 32, V =12V, V =1.2V, ƒ IN OUT 8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise. 1.30 1.25 1.20 1.15 1.10 1.05 ...

Page 11

TYPICAL OPERATING CHARACTERISTICS (CONTINUED) Circuit of Figure 32, V =12V, V =1.2V, ƒ IN OUT 8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise. 40ns/div Figure 19: Body-Braking® Delays 100ns/div ...

Page 12

TYPICAL OPERATING CHARACTERISTICS (CONTINUED) Circuit of Figure 32, V =12V, V =1.2V, ƒ IN OUT 8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise. 4ms/div Figure 25: Diode Emulation Setup ...

Page 13

... BODY-BRAKING® MODE International Rectifier’s Body-Braking® operation mode in which two MOSFETs are turned off. When the synchronous MOSFET is off, the higher voltage across the Shottky diode in parallel helps discharging the inductor current faster, which reduces the output voltage overshoot. The Body-Braking® ...

Page 14

MOSFET, allowing the switch node to float. This is in contrast to the Body-Braking® mode shown in Figure 23, where GATEL follows PWM input. The Schottky diode in parallel with the synchronous MOSFET ...

Page 15

L over the inductor DCR ( the two time constants match, the voltage across proportional to the current through L, and the sense circuit can be treated as if only ...

Page 16

If any of the application condition, i.e. input voltage, output voltage, switching frequency, VCC MOSFET driver voltage or inductance, is different from those of Figure 8, a set of normalized power loss curves should be used. Obtain the normalizing factors ...

Page 17

... In very high duty cycle applications sufficient time must be provided for replenishment of the Bootstrap capacitor for the control MOSFET drive. LAYOUT EXAMPLE Contact International Rectifier for a layout example suitable for your specific application. VCC IR3553 ...

Page 18

... Contact International Rectifier to receive an electronic PCB Library file in Cadence Allegro or CAD DXF/DWG format. March 12, 2012 | FINAL DATASHEET 18 40A Integrated PowIRstage®  Center pad land length and width should be equal to maximum part pad length and width.  ...

Page 19

... At the inside corner of the solder resist where the lead land groups meet recommended to provide a fillet so a solder resist width of ≥ 0.17mm remains. * Contact International Rectifier to receive an electronic PCB Library file in Cadence Allegro or CAD DXF/DWG format. March 12, 2012 | FINAL DATASHEET 19 40A Integrated PowIRstage® ...

Page 20

... The low power signal stencil lead land apertures should therefore be shortened in length to keep area ratio of 65% to 75% while centered on lead land. * Contact International Rectifier to receive an electronic PCB Library file in Cadence Allegro or CAD DXF/DWG format. March 12, 2012 | FINAL DATASHEET 20 40A Integrated PowIRstage® ...

Page 21

MARKING INFORMATION Site / Date / Marking Code PACKAGE INFORMATION March 12, 2012 | FINAL DATASHEET 21 40A Integrated PowIRstage® 3553M ? YWW ? xxxxx Lot Code Figure 36: PQFN 4mm x 6mm Figure 37: PQFN 4mm x 6mm IR3553 ...

Page 22

IR WORLD HEADQUARTERS: March 12, 2012 | FINAL DATASHEET 22 40A Integrated PowIRstage® Data and specifications subject to change without notice. This product will be designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web ...

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