IRMCK171TR International Rectifier, IRMCK171TR Datasheet
IRMCK171TR
Specifications of IRMCK171TR
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IRMCK171TR Summary of contents
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... MCE JTAG-based emulator tools are supported for 8051 software development including an OTP programmer. IRMCK171 comes pin QFP package. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Product Summary Maximum clock input (f ...
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... SPI AC Timing.................................................................................................................................. 22 6.10 UART AC Timing .......................................................................................................................... 24 6.11 CAPTURE Input AC Timing ......................................................................................................... 25 6.12 OTP Programming Timing............................................................................................................ 26 6.13 JTAG AC Timing........................................................................................................................... 27 7 I/O Structure ............................................................................................................................................ 28 8 Pin List..................................................................................................................................................... 31 9 Package Dimensions............................................................................................................................... 33 10 Part Marking Information ..................................................................................................................... 34 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Table of Contents IRMCK171 2 ...
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... Table 17 SPI Write AC Timing........................................................................................................................ 22 Table 18 SPI Read AC Timing ....................................................................................................................... 23 Table 19 UART AC Timing ............................................................................................................................. 24 Table 20 CAPTURE AC Timing...................................................................................................................... 25 Table 21 OTP Programming Timing............................................................................................................... 26 Table 22 JTAG AC Timing.............................................................................................................................. 27 Table 23 Pin List ............................................................................................................................................. 32 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. List of Tables IRMCK171 3 ...
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... Figure 21 Analog operational amplifier output and AREF I/O structure ...................................................... 29 Figure 22 VPP programming pin I/O structure ............................................................................................... 30 Figure 23 VSS and AVSS pin structure.......................................................................................................... 30 Figure 24 VDD1 and VDDCAP pin structure.................................................................................................. 30 Figure 25 XTAL0/XTAL1 pins structure.......................................................................................................... 30 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. List of Figures IRMCK171 4 ...
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... ROM versions come in a 48-pin QFP package with identical pin configuration to facilitate PC board layout and transition to mass production. Figure 1 Typical Application Block Diagram Using IRMCK171 This document is the property of International Rectifier and may not be copied or distributed without expressed consent for permanent magnet motors as well as induction ...
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... P1.3/SYNC/SCK 7 P1.4/CAP VDD1 8 9 VSS VDDCAP 10 P2.0/NMI 11 P3.2/INT0 This document is the property of International Rectifier and may not be copied or distributed without expressed consent (Top View Figure 2 Pinout of IRMCK171 IRMCK171 38 37 PWMVH 36 PWMWH ...
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... Inverse Clark transformation o Vector rotator o Bit latch o Peak detect o Transition o Multiply-divide (signed and unsigned) o This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Mini-Motion Control Engine (MiniMCE) Program ROM/RAM 32kB Dual Port RAM 8bit 2kbyte CPU ...
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... Unbuffered seven channels (0 – 1.2V input) JTAG port (4 pins three channels of analog output (8 bit PWM) o UART C/SPI port o 32K byte OTP program ROM o 2K byte data RAM o This document is the property of International Rectifier and may not be copied or distributed without expressed consent. IRMCK171 8 ...
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... Interface TDO & Emulation) RESET RESET System OTP P1.5/VPP Programming Voltage (6.5V) VDD1 3.3V VSS This document is the property of International Rectifier and may not be copied or distributed without expressed consent. System clock Motion Control Modules Dual Port Memory (2kB) & Motion MCE Control Memory ...
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... Input/output port 1.3, can be configured as SYNC output or SPI clock output, needs to be pulled up to VDD1 in order to boot from I P3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select 1 This document is the property of International Rectifier and may not be copied or distributed without expressed consent clock output, or SPI data 2 ...
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... Test Interface Group P5.2/TMS JTAG test mode input or input/output digital port TDO JTAG data output P5.1/TDI JTAG data input, or input/output digital port TCK JTAG test clock This document is the property of International Rectifier and may not be copied or distributed without expressed consent. IRMCK171 11 ...
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... Power consumption D Note 1) The value is based on the condition of MCE clock=126MHz, 8051 clock 31.5MHz with a actual motor running by a typical MCE application program and 8051 code. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Min Typ -0 ...
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... High level output OH2 current Note: (1) Data guaranteed by design. (2) Applied to SCL/SO-SI, SDA/CS0 pins. (3) Applied to all digital I/O pins except SCL/SO-SI and SDA/CS0 pins. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Min Typ 3.0 V 3.3 V 6.70V 6.75V -0 ...
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... Rejection Ratio I Op amp output source SRC current I Op amp output sink SNK current Note: (1) Data guaranteed by design. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Min Typ DDCAP Table 4 PLL DC Characteristics Min Typ ...
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... Load regulation (V -0. PSRR Power Supply Rejection Ratio Table 8 CMEXT and AREF DC Characteristics Note: (1) Data guaranteed by design. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Min Typ 2.78 V 3.04 V 2. Table 6 UVcc DC Characteristics Min ...
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... Short time jitter S D Duty cycle T PLL lock time LOCK Note: (1) Data guaranteed by design This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Min Typ 3.2 MHz 4 MHz 32 MHz 50 MHz F ÷ 256 - CLKIN - 200 psec ...
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... Symbol Parameter T Conversion time CONV T Sample/Hold maximum HOLD hold time Note: (1) Data guaranteed by design. Input Voltage Voltage droop This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Min Typ - - - - Table 10 A/D Converter AC Characteristics S/H Voltage t SAMPLE T HOLD Figure 4 Voltage droop and S/H hold time ...
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... Figure 5. Here only the single shunt current amplifier is show but all op amp outputs should be loaded with this capacitor. IRMCK171 IC Figure 5 A capacitor of 47pF is recommended at the output pin of all op amps. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Min Typ Max - 10 V/μ ...
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... SYNC to AIN0-5 analog dSYNC2 input conversion time t SYNC to PWM output dSYNC3 delay time Note: (1) AIN1 through AIN5 channels are converted once every 6 SYNC events This document is the property of International Rectifier and may not be copied or distributed without expressed consent. t wSYNC t dSYNC1 t dSYNC2 t dSYNC3 ...
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... Itrip AC Timing Unless specified 25˚C. Symbol Parameter t Itrip propagation delay ITRIP This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Figure 7 Gatekill timing Min Typ Table 13 GATEKILL to SVPWM AC Timing Figure 8 ITRIP timing ...
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... I C read hold time I2RHOLD Note read setup time is determined by the programmable filter time applied to I This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Figure 9 Interrupt timing Min Typ Max ...
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... CLK falling edge to data WRDELAY delay time t CS high time between two CSHIGH consecutive byte transfer t CS hold time CSHOLD This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Figure 11 SPI write timing Min Typ Max 1/2 ...
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... SPI read data hold time RDHOLD t CS high time between two CSHIGH consecutive byte transfer t CS hold time CSHOLD This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Figure 12 SPI read timing Min Typ Max ...
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... Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/ three sampled values do not agree, then UART noise error is generated. BAUD This document is the property of International Rectifier and may not be copied or distributed without expressed consent. T BAUD Data and Parity Bit ...
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... CAPTURE falling edge to CRDELAY capture register latch time t CAPTURE rising edge to CLDELAY capture register latch time t CAPTURE input interrupt INTDELAY latency time This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Figure 14 CAPTURE timing Min Typ ...
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... Unless specified 25˚C. Symbol Parameter T VPP Setup Time VPS T VPP Hold Time VPH This document is the property of International Rectifier and may not be copied or distributed without expressed consent. VPS T VPH Figure 15 OTP programming timing Min Typ 10 15 Table 21 OTP Programming Timing IRMCK171 6 ...
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... JHIGH t TCK Low Period JLOW t TCK to TDO propagation delay CO time t TDI/TMS setup time JSETUP t TDI/TMS hold time JHOLD This document is the property of International Rectifier and may not be copied or distributed without expressed consent. T JCLK t JLOW t JHIGH JSETUP t JHOLD Figure 16 JTAG timing ...
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... The following figure shows the digital I/O structure except the motor PWM output Internal digital circuit Low true logic PIN Figure 18 All digital I/O except motor PWM output This document is the property of International Rectifier and may not be copied or distributed without expressed consent. VDD1 (3.3V) 70k 6.0V 270 6 ...
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... The following figure shows the analog input structure. The following figure shows all analog operational amplifier output pins and AREF pin I/O structure. Figure 21 Analog operational amplifier output and AREF I/O structure This document is the property of International Rectifier and may not be copied or distributed without expressed consent. VDD1 (3.3V) ...
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... The following figure shows the VSS and AVSS pins structure The following figure shows the VDD1 and VDDCAP pin structure The following figure shows the XTAL0 and XTAL1 pins structure This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 270 PIN 8 ...
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... AIN5O 27 AVSS 28 VDDCAP 29 VDD1 30 VSS 31 P3.1/AOPWM2 32 PWMWL This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Internal Pull- Pin up /Pull- Type down I O I/O Discrete programmable I/O or Timer/Counter 2 input 2 I clock output (open drain, need pull up) or SPI data ...
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... P5.1/TDI 44 TCK 45 RESET 46 P1.1/RXD 47 P1.1/RXD 48 P3.3/INT1 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Internal Pull- Pin up /Pull- Type down 58 kΩ Pull O PWM gate drive for phase V low side, configurable down 58 kΩ Pull ...
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... Package Dimensions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. IRMCK171 33 ...
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... IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 Sales Offices, Agents and Distributors in Major Cities Throughout the World. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. http://www.irf.com Data and specifications subject to change without notice. 6/16/2006 ...