TLE 8203E Infineon Technologies, TLE 8203E Datasheet - Page 5
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TLE 8203E
Manufacturer Part Number
TLE 8203E
Description
Manufacturer
Infineon Technologies
Datasheet
1.TLE_8203E.pdf
(33 pages)
Specifications of TLE 8203E
Packages
PG-DSO-36
Ipeak
6.25 A for OUT 7
Inhibit
Y
Iq (typ)
0.2 µA2.5 µA
Mounting
SMT
Technology
BCD
3
3.1
Figure 2
3.2
Pin
cooling
tab
1, 18,
19, 36
2
3
4, 26,
30, 33
5
6
7
Final Data Sheet
Symbol
GND
GND
OUT5
OUT6
V
INH
PWM1
PWM2
S
Pin Configuration
Pin Assignment
Pin Configuration PG-DSO-36-50
Pin Definitions and Functions
Function
Cooling Tab; internally connected to GND;
To reduce thermal resistance, place cooling areas and thermal vias on PCB.
Ground; internally connected to cooling tab (exposed pad).
Power-Output of Half-Bridge output 5; DMOS half-bridge (mirror position).
Power-Output of Half-Bridge output 6; DMOS half-bridge (mirror position).
Power Supply; needs decoupling capacitors to GND. > 47 F electrolytic in parallel
with 100 nF ceramic is recommended. All
Inhibit; active low. Sets the device in sleep mode with low current consumption
when left open or pulled to LOW. Has an internal pull-down current source.
Logic Input for Direct Power Stage Control; direct input to control the high-side
switches selected by the SPI xsel1 bits in control register CtrlReg01.
Logic Input for Direct Power Stage Control; direct input to control the switches
selected by the SPI xsel2 bits in control register CtrlReg11.
5
V
S
pins must be connected externally.
Rev. 1.0, 2009-02-04
Pin Configuration
TLE 8203E