CA3130 Intersil Corporation, CA3130 Datasheet
CA3130
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CA3130 Summary of contents
Page 1
... Data Sheet 15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output CA3130A and CA3130 are op amps that combine the advantage of both CMOS and bipolar transistors. Gate-protected P-Channel MOSFET (PMOS) transistors are used in the input circuit to provide very-high-input impedance, very-low-input current, and exceptional speed performance ...
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... Maximum Output Current I + (Source (Sink Supply Current CA3130, CA3130A Thermal Information Thermal Resistance (Typical, Note 2) PDIP Package . . . . . . . . . . . . . . . . . . . SOIC Package . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature (Plastic Package 150 Maximum Storage Temperature Range . . . . . . . . . -65 Maximum Lead Temperature (Soldering 10s 300 (SOIC - Lead Tips Only ...
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... Input Current Common-Mode Rejection Ratio Large-Signal Voltage Gain Common-Mode Input Voltage Range Supply Current Power Supply Rejection Ratio NOTE: 4. Operation not recommended for temperatures below 25 3 CA3130, CA3130A SYMBOL TEST CONDITIONS 10kΩ Across Terminals 4 and and 1MHz ...
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... CMOS digital circuits in Comparator applications). Input Stage The circuit of the CA3130 is shown in the schematic diagram. It consists of a differential-input stage using PMOS field-effect transistors (Q transistors (Q with resistors R ...
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... Q and Second-Stage Most of the voltage gain in the CA3130 is provided by the second amplifier stage, consisting of bipolar transistor Q and its cascade-connected load resistance provided by PMOS transistors Q and Q . The source of bias potentials 3 5 for these PMOS transistors is subsequently described. Miller Effect compensation (roll-off) is accomplished by simply connecting a small capacitor between Terminals 1 and 8 ...
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... Because the gate- protection network functions connected to Terminal 4 potential, and the Metal Can case of the CA3130 is also internally tied to Terminal 4, input Terminal 3 is essentially “guarded” from spurious leakage currents. ...
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... Q R series-connected transistors Q L The two preceding stages in the CA3130, however, continue to draw modest supply-current (see the lower curve in Figure 20) even though the output stage is strobed off. Figure 6A shows a dual-supply arrangement for the output stage that can also be strobed off, assuming R potential of Terminal 8 down to that of Terminal 4 ...
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... VOLTAGE OUTPUT series and parallel combinations of 806,000Ω resistors from the same manufacturing lot. 30.1kΩ A single 15V supply provides a positive bus for the CA3130 0.01 µF follower amplifier and feeds the CA3085 voltage regulator. A “scale-adjust” function is provided by the regulator output control, set to a nominal 10V level in this system. The line- 1kΩ ...
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... FIGURE 8B. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING SETTLING TIME (MEASUREMENT MADE WITH TEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER) FIGURE 8. SPLIT SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS 9 CA3130, CA3130A 10kΩ 2kΩ 25pF FIGURE 9A. OUTPUT WAVEFORM WITH INPUT SIGNAL RAMPING (2V/DIV., 500µs/DIV.) Top Trace: Output; 5V/Div., 200µs/Div. ...
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... VOLTAGE 62 REGULATOR +15V 1 2 +10.010V CA3085 8 3 22. REGULATED + 4 2µF VOLTAGE 1K - 25V 0.001µF 3.83k 1% FIGURE 10. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3130 R 2 2kΩ 4kΩ CA3130 20pF OFFSET ADJUST Gain = ------ - = X = ------------------------------------- ...
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... CA3086 10 INPUT REGULATION (NO LOAD TO FULL LOAD): <0.01% INPUT REGULATION: 0.02%/V HUM AND NOISE OUTPUT: <25µ 100kHz FIGURE 13. VOLTAGE REGULATOR CIRCUIT (0V TO 13V AT 40mA) 11 CA3130, CA3130A 6V INPUT; P-P BW (-3dB) = 360kHz 0.3V P-P BW (-3dB) = 320kHz +DC OUTPUT + 100 5µF kΩ - FIGURE 12B. PEAK NEGATIVE DETECTOR CIRCUIT FIGURE 12 ...
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... CURRENT LIMIT ADJUST 3 2N5294 + 43kΩ 1000pF 100µ ERROR OUTPUT: AMPLIFIER 8 0.1 TO 50V 10kΩ CA3130 - 2 4 8.2kΩ Transistor are used to bias the CA3130 to the mid-point of the 2 is the feedback resistor. The pulse the desired . A 1 ...
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... In the circuit of Figure 17, three CMOS transistor- pairs in a single CA3600E (see Note 12) lC array are shown parallel connected with the output stage in the CA3130. In the Class A mode of CA3600E shown, a typical device consumes 20mA of supply current at 15V operation. This arrangement boosts the current-handling capability of the CA3130 output stage by about 2 ...
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... BW (-3 dB) = 50kHz 510kΩ NOTES: 11. Transistors and 12. See file number 619. FIGURE 17. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3130 Typical Performance Curves 150 LOAD RESISTANCE = 2kΩ 140 130 120 110 100 90 80 -100 -50 ...
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... NEGATIVE SUPPLY VOLTAGE = POSITIVE SUPPLY VOLTAGE = 5V 1 0.1 0.01 0.001 0.001 0.01 0.1 MAGNITUDE OF LOAD CURRENT (mA) FIGURE 22. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR ( LOAD CURRENT 8 15 CA3130, CA3130A (Continued FIGURE 21. QUIESCENT SUPPLY CURRENT vs SUPPLY 15V 10V 0.01 0.001 1.0 10 100 FIGURE 23 ...
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... B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 16 CA3130, CA3130A E8.3 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE SYMBOL ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 CA3130, CA3130A M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC ...