CD4015BT Intersil Corporation, CD4015BT Datasheet

CD4015BT

Manufacturer Part Number

CD4015BT

Description

Manufacturer

Intersil Corporation

Datasheet

1.CD4015BT.pdf (3 pages)

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CMOS Dual 4-Stage Static Shift Register

With Serial Input/Parallel Output

Intersil’s Satellite Applications Flow

tested and guaranteed to 100kRAD total dose. These QML

Class T devices are processed to a standard ﬂow intended

to meet the cost and shorter lead-time needs of large

volume satellite manufacturers, while maintaining a high

level of reliability.

CD4015BT consists of two identical, independent, 4-stage

serial-input/parallel output registers. Each register has

independent CLOCK and RESET inputs as well as a single

serial DATA input. “Q” outputs are available from each of the

four stages on both registers. All register stages are D type,

master-slave ﬂip-ﬂops. The logic level present at the DATA

input is transferred into the ﬁrst register stage and shifted

over one stage at each positive-going clock transition.

Resetting of all stages is accomplished by a high level on the

reset line. Register expansion to 8 stages using one

CD4015BT, or to more than 8 stages using additional

CD4015BT’s is possible.

Speciﬁcations

Speciﬁcations for Rad Hard QML devices are controlled by

the Defense Supply Center in Columbus (DSCC). The SMD

numbers listed below must be used when ordering.

Detailed Electrical Speciﬁcations for the CD4015BT are

contained in SMD 5962-96624. A “hot-link” is provided from

our website for downloading.

www.intersil.com/spacedefense/newsafclasst.asp

Intersil’s Quality Management Plan (QM Plan), listing all

Class T screening operations, is also available on our

website.

www.intersil.com/quality/manuals.asp

Ordering Information

NOTE:

distribution, or 450 units direct.

5962R9662401TEC

5962R9662401TXC

ORDERING

Minimum order quantity for -T is 150 units through

NUMBER

CD4015BDTR

CD4015BKTR

NUMBER

PART

Data Sheet

(SAF) devices are fully

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

-55 to 125

RANGE

TEMP.

(

CLOCK B

Features

• QML Class T, Per MIL-PRF-38535

• Radiation Performance

• Medium Speed Operation 12MHz (typ.) Clock Rate at V

• Fully Static Operation

• 8 Master-Slave Flip-Flops Plus Input and Output Buffering

• 100% Tested For Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Standardized Symmetrical Output Characteristics

Pinouts

RESET A

DATA A

www.intersil.com or 407-727-9207

- Gamma Dose ( ) 1 x 10

- SEP Effective LET > 75 MEV/gm/cm

- V

Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.

Q4B

Q3A

Q2A

Q1A

= 10V

CLOCK B

RESET A

CD4015BT (FLATPACK), CDFP4-F16

DATA A

July 1999

CD4015BT (SBDIP), CDIP2-T16

Q4B

Q3A

Q2A

Q1A

TOP VIEW

RAD(Si)

File Number 4621.1

CD4015BT

DATA B

RESET B

Q1B

Q2B

Q3B

Q4A

CLOCK A

Intersil Corporation 1999

DATA B

RESET B

Q1B

Q2B

Q3B

Q4A

CLOCK A

Related parts for CD4015BT

CD4015BT Summary of contents

Page 1

... Resetting of all stages is accomplished by a high level on the reset line. Register expansion to 8 stages using one CD4015BT more than 8 stages using additional CD4015BT’s is possible. Speciﬁcations Speciﬁcations for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC) ...

Page 2

... Functional Diagram Logic Diagram DATA 15 † (7) CLOCK 1 † (9) RESET 14 † ( † ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK 2 CD4015BT DATA CLOCK STAGE RESET DATA CLOCK STAGE ...

Page 3

... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3 CD4015BT PASSIVATION: Type: Phosphorus Doped Silox (S Thickness: 13k WORST CASE CURRENT DENSITY: < 2.0e5 A/cm TRANSISTOR COUNT First DD PROCESS: Bulk CMOS CD4015BT 80mils Å ...

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