LURF43740/P1-PF Agere Systems, LURF43740/P1-PF Datasheet
LURF43740/P1-PF
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LURF43740/P1-PF Summary of contents
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July 2000 QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/ FX Introduction The LU3X54FT is a four-channel, single-chip com- plete transceiver designed specifically for dual-speed 10Base-T, 100Base-TX, and 100Base-FX repeaters and switches. It supports simultaneous operation in three separate IEEE standard modes: ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Contents Introduction ............................................................................................................................................................... 1 Features ................................................................................................................................................................... 1 10 Mbits/s Transceiver ........................................................................................................................................... 1 100 Mbits/s TX Transceiver ................................................................................................................................... 1 100 Mbits/s FX Transceiver ................................................................................................................................... 4 General .................................................................................................................................................................. 4 Description ............................................................................................................................................................... 4 Bused MII Mode..................................................................................................................................................... 4 Clocking ................................................................................................................................................................. ...
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Data Sheet July 2000 Tables Table 19. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions...................................................36 Table 20. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions ............................................37 Table 21. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions ..............................................38 Table 22. MR31—Device-Specific Register ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Features (continued) 100 Mbits/s FX Transceiver Compatible with IEEE 802.3U 100Base-FX standard Reuses existing twisted-pair I/O pins for compatible fiber-optic transceiver pseudo-ECL (PECL) data: — No additional data pins required — Reuses existing LU3X54FT pins for ...
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Data Sheet July 2000 Description (continued) Bused MII Mode (continued) The bused mode has two additional submodes of operation: Separate Bused MII Mode. This mode is designed to operate with two independent repeater ICs, one repeater operating at 100 Mbits/s ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Description (continued) Clocking (continued) Either the on-chip 20 MHz clock synthesizer (default clock) can be used, or H-DUPLED[A]/CLK20_SEL (pin 198) can be pulled high (sensed on powerup and reset) to select the external 20 MHz clock ...
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Data Sheet July 2000 Description (continued) Functional Block Diagrams Device Overview MII/SERIAL INTERFACE MII/SERIAL INTERFACE MII/SERIAL INTERFACE MII/SERIAL INTERFACE 25 MHz LSCLK 125 MHz DPLL 25 MHz 20 MHz 25 MHz CRYSTAL 10 MHz 20 MHz Lucent Technologies Inc. QUAD-FET ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Description (continued) Functional Block Diagrams Single-Channel Detail Functions 100 OFF TXD[3:0] 4B/5B ENCODER CRS COL TX STATE MACHINE RXD[3:0] RX_DV RX_ER/RXD[4] MII RX_CLK CIM TX_CLK TXD[3:0] 5B/4B DECODER TX_EN TX_ER/TXD[4] FAR-END FAULT DETECT REF10 RX_CLK RXD[0] ...
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Data Sheet July 2000 Description (continued) Application Diagrams Single-Channel Twisted-Pair Interface TPOUT+ LU3X54FT TPOUT– TPIN+ TPIN– MHz Figure 3. Typical Single-Channel Twisted-Pair (TP) Interface Lucent Technologies Inc. QUAD-FET for 10Base-T/100Base-TX/FX V DDO 1:1 ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Description (continued) Application Diagrams (continued) Single-Channel Fiber-Optic Interface TPOUT+ LU3X54FT TPOUT– FOSD TPIN+ TPIN– MHz Figure 4. Typical Single-Channel Fiber-Optic Interface 10 V DDA V DDO 50 220 82 ...
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Data Sheet July 2000 Description (continued) Block Diagrams Smart Bused MII Mode 10/100 Mbits/s SMART REPEATER Figure 5. Smart 10/100 Mbits/s Bused MII Mode Lucent Technologies Inc. QUAD-FET for 10Base-T/100Base-TX/FX RX_CLK10 RX_CLK10 RXD_10 RXD_10 TX_CLK10 TX_CLK10 TXD_10 TXD_10 CRS_10/100 4 ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Description (continued) Block Diagrams (continued) Separate Bused MII Mode 10 Mbits/s REPEATER 100 Mbits/s REPEATER MANAGEMENT Figure 6. Separate 10/100 Mbits/s Bused MII Mode 12 RX_CLK10 RX_CLK10 RXD_10 RXD_10 TX_CLK10 TX_CLK10 TXD_10 TXD_10 COL_10 4 COL_10 ...
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Data Sheet July 2000 Pin Information Pin Diagram for Normal MII Mode GNDA 1 FOSD[C] 2 FOSD[D] 3 VDDA 4 TPIN+/FOIN+[D] 5 TPIN–/FOIN–[D] 6 GNDA 7 VDDA 8 TPIN+/FOIN+[C] 9 TPIN–/FOIN–[C] 10 GNDA 11 VDDA 12 BGREF0 13 GNDA 14 ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Pin Information (continued) Pin Diagram for Bused MII Mode GNDA 1 FOSD[C] 2 FOSD[D] 3 VDDA 4 TPIN+/FOIN+[D] 5 TPIN–/FOIN–[D] 6 GNDA 7 VDDA 8 TPIN+/FOIN+[C] 9 TPIN–/FOIN–[C] 10 GNDA 11 VDDA 12 BGREF0 13 GNDA ...
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Data Sheet July 2000 Pin Information (continued) Pin Maps Table 2. LU3X54FT Pin Maps Normal Mode Pins Bused Mode Pins RXD[D][3:0] CRS_10[D:A] CRS[D:A] CRS_100[D:A] TXD[C][3:0] RX_EN10[D:A] MII_EN[D:A] RX_EN100[D:A] TXD[3:0][D] TX_EN10[D:A] TX_EN[D:A] TX_EN100[D:A] RXD[3:0][C] COL_10[D:A] COL[D:A] COL_100[D:A] SPEEDLED[C] SMART_MODE_SELECT SPEEDLED[B] BUSED_MII_MODE ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Pin Information (continued) Pin Descriptions This section describes the LU3X54FT signal pins. Note that any register bit referenced includes the register num- ber and bit position. For example, register bit [29.8] is register 29, bit 8. ...
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Data Sheet July 2000 Pin Information (continued) Pin Descriptions (continued) Table 3. MII/Serial Interface Pins in Normal MII Mode (Four Separate MII Ports) (continued) Pin Signal Type 98 TX_CLK[D:A] 65 148 125 93, 60 TXD[3:0][D:A] 143, 120 92, 59 142, ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Pin Information (continued) Pin Descriptions (continued) When operating in bused MII mode, 100 Mbits/s data is bused to MII port A, and 10 Mbits/s data is bused to MII port B. Table 4. MII/Serial Interface Pins ...
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Data Sheet July 2000 Pin Information (continued) Pin Descriptions (continued) When operating in bused MII mode, 100 Mbits/s data is bused to MII port A, and 10 Mbits/s data is bused to MII port B. Table 4. MII/Serial Interface Pins ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Pin Information (continued) Pin Descriptions (continued) When operating in bused MII mode, 100 Mbits/s data is bused to MII port A, and 10 Mbits/s data is bused to MII port B. Table 4. MII/Serial Interface Pins ...
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Data Sheet July 2000 Pin Information (continued) Pin Descriptions (continued) When operating in bused MII mode, 100 Mbits/s data is bused to MII port A, and 10 Mbits/s data is bused to MII port B. Table 4. MII/Serial Interface Pins ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Pin Information (continued) Pin Descriptions (continued) Table 5. MII Management Pins Pin Signal Type 113 MDC I 112 MDIO I/O 53 MASK_STAT_INT O Table 6. 10/100 Mbits/s Twisted-Pair (TP) Interface Pins Pin Signal Type 5 TPIN+/ ...
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Data Sheet July 2000 Pin Information (continued) Pin Descriptions (continued) Table 7. Miscellaneous Pins Pin Signal 81 CKREF 184 ATEST[B:A] 183 197 AUTO_EN 1, 7, GND/V SS 11, 14, 18, 22, 24, 26, 29, 31, 35, 39, 41, 45, 49, ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Pin Information (continued) Pin Descriptions (continued) Table 7. Miscellaneous Pins (continued) Pin Signal 43 ISET_100 114 REF10 27 CLK20 166 TXLED[D]/ CARIN_EN 165 TXLED[C]/ ENC_DEC_BYPASS 164 TXLED[B]/ SCRAM_DESC_BYPASS 162 TXLED[A]/ REF_SEL 24 Type I Current Set ...
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Data Sheet July 2000 Pin Information (continued) Pin Descriptions (continued) Table 7. Miscellaneous Pins (continued) Pin Signal 171—168 RXLED[D:A]/ FX_MODE_EN[D:A] 176—173 COLED[D:A] 190 LINKLED[D]/ PHYADD[2] 189 LINKLED[C]/ PHYADD[1] 188 LINKLED[B]/ PHYADD[0] 187 LINKLED[A]/ NO_LP Lucent Technologies Inc. QUAD-FET for 10Base-T/100Base-TX/FX ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Pin Information (continued) Pin Descriptions (continued) Table 7. Miscellaneous Pins (continued) Pin Signal 194 SPEEDLED[D]/ SPEED 193 SPEEDLED[C]/ SMART_MODE_SELECT 192 SPEEDLED[B]/ BUSED_MII_MODE 26 Type I/O Speed LED[D]. This pin indicates the operating speed of port D ...
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Data Sheet July 2000 Pin Information (continued) Pin Descriptions (continued) Table 7. Miscellaneous Pins (continued) Pin Signal 191 SPEEDLED[A]/ ISOLATE_MODE 201 H_DUPLED[D]/ FULL_DUP 198 H_DUPLED[A]/ CLK20_SEL 87 LSCLK/XTALIN 88 XTALOUT 55 MODE[4:0] 207—204 Lucent Technologies Inc. QUAD-FET for 10Base-T/100Base-TX/FX Type ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Pin Information (continued) Pin Descriptions (continued) Table 7. Miscellaneous Pins (continued) Pin Signal 203 RESET 199 H_DUPLED[B]/ CRS_SEL 200 H_DUPLED[C]/ SERIAL_SEL Type I Full Chip Reset. Reset must be asserted high for at ...
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Data Sheet July 2000 MII Station Management Basic Operations The primary function of station management is to trans- fer control and status information about the LU3X54FT to a management entity. This function is accomplished by the MDC clock input, which ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX MII Station Management Management Registers (MR) Register Overview The MII management 16-bit register (MR) set is implemented as described in the table below. Table 10. MII Management Registers (MR) Register Symbol Address 0 MR0 1 MR1 ...
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Data Sheet July 2000 MII Station Management Management Registers (MR) This section provides a detailed discussion of each management register and its bit definitions. Table 11. MR0—Control Register Bit Descriptions 1 2 Register/Bit Type 0.15 (SW_RESET) R/W 0.14 (LOOPBACK) R/W ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX MII Station Management Management Registers (MR) Table 12. MR1—Status Register Bit Descriptions 1 2 Register/Bit Type 1.15 (T4ABLE) R 100Base-T4 Ability. This bit will always Not able. 1: Able. 1.14 (TXFULDUP) R ...
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Data Sheet July 2000 MII Station Management Management Registers (MR) Table 13. MR2, 3—PHY Identifier Registers (1 and 2) Bit Descriptions 1 Register/Bit Type 2.15:0 (OUI[3:18]) R 3.15:10 (OUI[19:24]) R 3.9:4 (MODEL[5:0]) R 3.3:0 (VERSION[3:0 Note that the ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX MII Station Management Management Registers (MR) Table 15. MR5—Autonegotiation Link Partner (LP) Ability Register (Base Page) Bit Descriptions 1 Register/Bit Type 5.15 (LP_NEXT_PAGE) R 5.14 (LP_ACK) R 5.13 (LP_REM_FAULT) R 5.12:5 R (LP_TECH_ABILITY) 5.4:0 (LP_SELECT) R ...
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Data Sheet July 2000 MII Station Management Management Registers (MR) Table 17. MR6—Autonegotiation Expansion Register Bit Descriptions 1 Register/Bit Type 6.15:5 (RESERVED) R 6.4 (PAR_DET_FAULT) R/LH 6.3 R (LP_NEXT_PAGE_ABLE) 6.2 (NEXT_PAGE_ABLE) R 6.1 (PAGE_REC) R/LH 6.0 (LP_NWAY_ABLE Note ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX MII Station Management Management Registers (MR) Table 19. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions 1 2 Register/Bit Type 28.15:9 (R28[15:9]) R 28.8 (BAD_FRM) R/LH 28.7 (CODE) R/LH 28.6 (APS) R 28.5 (DISCON) R/LH 28.4 (UNLOCKED) ...
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Data Sheet July 2000 MII Station Management Management Registers (MR) Table 20. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions 1 Register/Bit Type 29.15 (LOCALRST) R/W 29.14 (RST1) R/W 29.13 (RST2) R/W 29.12 (100OFF) R/W 29.11 (RESERVED) R/W 29.10 (CRS_SEL) ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX MII Station Management Management Registers (MR) Table 21. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions 1 2 Register/Bit Type 30.15:7 (R28[15:7]) R/W 30.6 (CLK_SEL) R/W 30.5 (HBT_EN) R/W 30.4 (ELL_EN) R/W 30.3 (APF_DIS) R/W 30.2 ...
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Data Sheet July 2000 MII Station Management Management Registers (MR) Table 22. MR31—Device-Specific Register 4 (Quick Status) Bit Descriptions 1 2 Register/Bit Type 31.15 (ERROR) R Receiver Error. When this bit indicates that a receive error ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX MII Station Management Unmanaged Operations The LU3X54FT allows the user to set some of the station management functions during powerup or reset by strap- ping outputs high or low through weak resistors ( Table ...
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Data Sheet July 2000 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Package and Thermal Characteristics The LU3X54FT is packaged in a 208-pin SQFP , plain plastic package (LU3X54FT-S208) or with an internal heat spreader (LU3X54FT-HS208). Both packages have identical dimensions and conform to the outline diagram in ...
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Data Sheet July 2000 Timing Characteristics (Preliminary) Table 29. MII Management Interface Timing (25 pF Load) Name Parameter t1 MDIO Valid to Rising Edge of MDC (setup) t2 Rising Edge of MDC to MDIO Invalid (hold) t3 MDC Falling Edge ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Timing Characteristics (Preliminary) Table 30. MII Data Timing (25 pF Load) Name t1 RXD[3:0], RX_ER, RX_DV Valid to RX_CLK High t2 RX_CLK High to RXD[3:0], RX_DV, RX_ER Invalid t3 RX_CLK High t4 RX_CLK Low t5 RX_CLK ...
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Data Sheet July 2000 Timing Characteristics (Preliminary) RX_CLK RXD[3:0] RX_DV RX_ER Figure 13. MII Timing Requirements for LU3X54FT Lucent Technologies Inc. QUAD-FET for 10Base-T/100Base-TX/FX (continued TX_CLK t7 TXD[3:0] TX_EN TX_ER t9 LSCLK TXD[3:0] TX_EN ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Timing Characteristics (Preliminary) Table 31. Serial 10 Mbits/s Timing for TPIN, CRS, and RX_CLK Name t15 TPIN Activity to CRS Assertion t16 TPIN Activity to RX_CLK Valid t17 IDL to CRS Deassertion t18 Dead Signal to ...
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Data Sheet July 2000 Timing Characteristics (Preliminary) Table 33. Serial 10 Mbits/s Timing for TX_EN, TPIN, and COL Name t24 Time to Assert COL; LU3X54FT Is Transmitting; Receive Activity Starts t25 Time to Deassert COL; LU3X54FT Is Transmitting; Receive Activity ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Timing Characteristics (Preliminary) Table 34. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD (25 pF Load) Name t29 RXD Setup Before RX_CLK Rising Edge t30 RXD Held Past RX_CLK Edge t31 RX_CLK ...
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Data Sheet July 2000 Timing Characteristics (Preliminary) Table 35. Serial 10 Mbits/s Timing for RX_CLK and TX_CLK (25 pF Load) Name t36 RX_CLK Low Pulse Width t37 RX_CLK High Pulse Width t38 TX_CLK Low Pulse Width t39 TX_CLK High Pulse ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Timing Characteristics (Preliminary) Table 36. 100 Mbits/s MII Transmit Timing Name t40 Rising Edge of TX_CLK Following TX_EN Assertion to CRS Assertion t41 Rising Edge of TX_CLK Following TX_EN Assertion to TPOUT t42 Rising Edge of ...
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Data Sheet July 2000 Timing Characteristics (Preliminary) Table 37. 100 Mbits/s MII Receive Timing Name t43 TPIN 1st Bit of J Receive Activity to CRS Asserted t44 TPIN Receive Activity to Receive Data Valid t45 TPIN Receive Activity Cease (1st ...
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LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Outline Diagram 208-Pin SQFP Dimensions are in millimeters. 30.60 ± 0.20 28.00 ± 0.20 PIN #1 IDENTIFIER ZONE 208 DETAIL A 0.50 TYP 52 157 156 28.00 ± 0.20 ± 0.20 105 104 ...
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Data Sheet July 2000 Ordering Information Device Code Comcode LU3X54FT-HS208 108193384 LU3X54FT-S208 108297334 *Refer to package and thermal characteristics Lucent Technologies Inc. QUAD-FET for 10Base-T/100Base-TX/FX Package 208-Pin SQFPH (Heat Spreader) 208-Pin SQFP LU3X54FT Temperature ...
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For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA ...