74ABT245CSCX Fairchild Semiconductor, 74ABT245CSCX Datasheet

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74ABT245CSCX

Manufacturer Part Number
74ABT245CSCX
Description
IC TRANSCVR TRI-ST 8BIT 20SOIC
Manufacturer
Fairchild Semiconductor
Series
74ABTr
Datasheets

Specifications of 74ABT245CSCX

Logic Type
Transceiver, Non-Inverting
Number Of Elements
1
Number Of Bits Per Element
8
Current - Output High, Low
32mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ABT245CSCX
Manufacturer:
FCS
Quantity:
20 000
© 1999 Fairchild Semiconductor Corporation
74ABT245CSC
74ABT245CSJ
74ABT245CMSA
74ABT245CMTC
74ABT245CPC
74ABT245
Octal Bi-Directional Transceiver with 3-STATE Outputs
General Description
The ABT245 contains eight non-inverting bidirectional buff-
ers with 3-STATE outputs and is intended for bus-oriented
applications. Current sinking capability is 64 mA on both
the A and B ports. The Transmit/Receive (T/R) input deter-
mines the direction of data flow through the bidirectional
transceiver. Transmit (active HIGH) enables data from A
Ports to B Ports; Receive (active LOW) enables data from
B Ports to A Ports. The Output Enable input, when HIGH,
disables both A and B ports by placing them in a HIGH Z
condition.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
MSA20
MTC20
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
DS010945
Features
Pin Descriptions
Bidirectional non-inverting buffers
A and B output sink capability of 64 mA, source
capability of 32 mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50 pF and 250 pF
loads
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
Guaranteed latchup protection
High impedance glitch-free bus loading during entire
power up and power down cycle
Non-destructive hot insertion capability
Disable time is less than enable time to avoid bus
contention
OE
T/R
A
B
Pin Names
0
0
–A
–B
Package Description
7
7
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
September 1991
Revised November 1999
Description
www.fairchildsemi.com

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74ABT245CSCX Summary of contents

Page 1

... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram © 1999 Fairchild Semiconductor Corporation Features Bidirectional non-inverting buffers A and B output sink capability of 64 mA, source ...

Page 2

Logic Symbol Logic Diagram www.fairchildsemi.com Truth Table Inputs Output OE T Bus B Data to Bus Bus A Data to Bus HIGH Z State H HIGH Voltage Level L LOW Voltage Level ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 5.0 mA Voltage Applied to Any Output in the ...

Page 4

DC Electrical Characteristics (SOIC package) Symbol Parameter V Quiet Output Maximum Dynamic V OLP OL V Quiet Output Minimum Dynamic V OLV OL V Minimum HIGH Level Dynamic Output Voltage OHV V Minimum HIGH Level Dynamic Input Voltage IHD V ...

Page 5

Skew (SOIC package) Symbol Parameter t Pin to Pin Skew OSHL (Note 10) HL Transitions t Pin to Pin Skew OSLH (Note 10) LH Transitions t Duty Cycle PS (Note 14) LH–HL Skew t Pin to Pin Skew OST (Note ...

Page 6

AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Amplitude 3.0V FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. Propagation Delay, Pulse Width Waveforms ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.fairchildsemi.com Package Number MTC20 10 ...

Page 11

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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