74LCX652MTCX Fairchild Semiconductor, 74LCX652MTCX Datasheet

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74LCX652MTCX

Manufacturer Part Number
74LCX652MTCX
Description
IC TXRX/REGISTER LV 5V 24TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LCXr
Datasheet

Specifications of 74LCX652MTCX

Logic Type
Registered Transceiver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
8
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2001 Fairchild Semiconductor Corporation
74LCX652WM
74LCX652MSA
74LCX652MTC
74LCX652
Low Voltage Transceiver/Register
with 5V Tolerant Inputs and Outputs
General Description
The LCX652 consists of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to the
HIGH logic level. Output Enable pins (OEAB, OEBA) are
provided to control the transceiver function.
The LCX652 is designed for low voltage (2.5V or 3.3V) V
applications with capability of interfacing to a 5V signal
environment.
The LCX652 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
MSA24
MTC24
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
DS011998
CC
Features
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
resistor is determined by the current-sourcing capability of the driver.
Pin Descriptions
A
CPAB, CPBA
SAB, SBA
OEAB, OEBA
0
5V tolerant inputs and outputs
2.3V
7.0 ns t
Power down high impedance inputs and outputs
Supports live insertion/withdrawal (Note 1)
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds 500 mA
ESD performance:
–A
24 mA output drive (V
Pin Names
Human body model
Machine model
7
Package Description
, B
3.6V V
PD
0
–B
max (V
7
CC
CC
through a pull-up resistor: the minimum value or the
A and B Inputs/3-STATE Outputs
Clock Inputs
Select Inputs
Output Enable Inputs
specifications provided
CC
200V
3.3V), 10 A I
CC
2000V
3.0V)
February 1994
Revised March 2001
Description
CC
www.fairchildsemi.com
max

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74LCX652MTCX Summary of contents

Page 1

... MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2001 Fairchild Semiconductor Corporation Features 5V tolerant inputs and outputs 2.3V 3 ...

Page 2

Logic Symbols Truth Table (Note 2) Inputs OEAB OEBA CPAB CPBA SAB ...

Page 3

Functional Description In the transceiver mode, data present at the HIGH imped- ance port may be stored in either the register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples below demonstrate ...

Page 4

Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 4 ...

Page 5

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...

Page 6

DC Electrical Characteristics Symbol Parameter I Quiescent Supply Current CC I Increase in I per Input CC CC Note 6: Outputs disabled or 3-STATE only. AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PHL t ...

Page 7

AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C t PLH t PZL t PZH Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable and Disable Times for Logic (Input Characteristics; ...

Page 8

Schematic Diagram Generic for LCX Family www.fairchildsemi.com 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number M24B Package Number MSA24 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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