74LCX16244MTDX Fairchild Semiconductor, 74LCX16244MTDX Datasheet

IC BUFF DVR 16BIT LOW V 48TSSOP

74LCX16244MTDX

Manufacturer Part Number
74LCX16244MTDX
Description
IC BUFF DVR 16BIT LOW V 48TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LCXr
Datasheet

Specifications of 74LCX16244MTDX

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
4
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Logic Family
74LCX
Number Of Channels Per Chip
Hexadecimal
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
85 C
Mounting Style
SMD/SMT
High Level Output Current
- 24 mA
Input Bias Current (max)
20 uA
Low Level Output Current
24 mA
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
16
Output Type
3-State
Propagation Delay Time
5.2 ns @ 2.7 V or 4.5 ns @ 3.3 V
Logic Device Type
Buffer/Line Driver, Non Inverting
Supply Voltage Range
2V To 3.6V
Logic Case Style
TSSOP
No. Of Pins
48
Operating Temperature Range
-40°C To +85°C
Supply Voltage Min
2V
Rohs Compliant
Yes
Dc
01+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LCX16244MTDX
74LCX16244MTDXTR

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Part Number:
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Quantity:
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Quantity:
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© 2005 Fairchild Semiconductor Corporation
74LCX16244G
(Note 2)(Note 3)
74LCX16244MEA
(Note 3)
74LCX16244MTD
(Note 3)
74LCX16244
Low Voltage 16-Bit Buffer/Line Driver
with 5V Tolerant Inputs and Outputs
General Description
The LCX16244 contains sixteen non-inverting buffers with
3-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus oriented transmit-
ter/receiver. The device is nibble controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The LCX16244 is designed for low voltage (2.5 or 3.3V)
V
environment.
The LCX16244 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Ordering Code:
Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
GTO
Order Number
CC
¥
applications with capability of interfacing to a 5V signal
is a trademark of Fairchild Semiconductor Corporation.
Package Number
BGA54A
MS48A
MTD48
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS012000
Features
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
resistor is determined by the current-sourcing capability of the driver.
5V tolerant inputs and outputs
2.3V to 3.6V V
4.5 ns t
Power down high impedance inputs and outputs
Supports live insertion/withdrawal (Note 1)
r
Uses patented noise/EMI reduction circuitry
Latch-up performance exceeds 500 mA
ESD performance:
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
24 mA output drive (V
Human body model
Machine model
Package Description
PD
max, 10
CC
CC
through a pull-up resistor: the minimum value or the
specifications provided
!
P
200V
A I
!
CC
CCQ
2000V
max
3.0V)
February 1994
Revised May 2005
www.fairchildsemi.com

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74LCX16244MTDX Summary of contents

Page 1

... Note 2: Ordering code “G” indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol ¥ GTO is a trademark of Fairchild Semiconductor Corporation. © 2005 Fairchild Semiconductor Corporation Features 5V tolerant inputs and outputs 2.3V to 3.6V V ...

Page 2

Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW –I Inputs –O Outputs ...

Page 3

Functional Description The LCX16244 contains sixteen non-inverting buffers with 3-STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but inde- pendent of the other. The control pins can be shorted together to obtain full ...

Page 4

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...

Page 5

DC Electrical Characteristics Symbol Parameter I Quiescent Supply Current Increase in I per Input CC CC Note 7: Outputs disabled or 3-STATE only. AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL t Data to Output PLH ...

Page 6

AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable and Disable Times for Logic (Input Characteristics; f =1MHz, t Symbol V mi ...

Page 7

Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide www.fairchildsemi.com Package Number BGA54A 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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