74LCX16646MTD Fairchild Semiconductor, 74LCX16646MTD Datasheet

no-image

74LCX16646MTD

Manufacturer Part Number
74LCX16646MTD
Description
IC TRANSCVR/REG 16BIT LV 56TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LCXr
Datasheet

Specifications of 74LCX16646MTD

Logic Type
Registered Transceiver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
8
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LCX16646MTDX
Manufacturer:
ON/安森美
Quantity:
20 000
© 2002 Fairchild Semiconductor Corporation
74LCX16646MEA
74LCX16646MTD
74LCX16646
Low Voltage 16-Bit Transceiver/Register
with 5V Tolerant Inputs and Outputs
General Description
The LCX16646 contains sixteen non-inverting bidirectional
registered bus transceivers with 3-STATE outputs, provid-
ing multiplexed transmission of data directly from the input
bus or from the internal storage registers. Each byte has
separate control inputs which can be shorted together for
full 16-bit operation.The DIR inputs determine the direction
of data flow through the device. The CPAB and CPBA
inputs load data into the registers on the LOW-to-HIGH
transition (see Functional Description).
The LCX16646 is designed for low voltage (2.5V or 3.3V)
V
environment.
The LCX16646 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number
CC
applications with capability of interfacing to a 5V signal
Package Number
MS56A
MTD56
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS012004
Features
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
resistor is determined by the current-sourcing capability of the driver.
Pin Descriptions
5V tolerant inputs and outputs
2.3V–3.6V V
5.2 ns t
Power down high impedance inputs and outputs
Supports live insertion/withdrawal (Note 1)
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds 500 mA
ESD performance:
Human Body Model
Machine Model
A
B
OE
CPAB
SAB
DIR
24 mA Output Drive (V
n
n
Pin Names
n
Package Description
n
n
, SBA
n
PD
, CPBA
max (V
n
CC
CC
through a pull-up resistor: the minimum value or the
n
specifications provided
CC
200V
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Output Enable Inputs
Clock Pulse Inputs
Select Inputs
Direction Control Inputs
2000V
3.3V), 20 A I
CC
February 1994
Revised August 2002
3.0V)
Description
CC
www.fairchildsemi.com
max

Related parts for 74LCX16646MTD

74LCX16646MTD Summary of contents

Page 1

... Package Number 74LCX16646MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LCX16646MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. ...

Page 2

Connection Diagram Truth Table (Note 2) Inputs OE DIR CPAB CPBA SAB ...

Page 3

Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com ...

Page 4

Functional Description In the transceiver mode, data present at the HIGH imped- ance port may be stored in either the register or both. The select (SAB , SBA ) controls can multiplex n n stored and real-time. ...

Page 5

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...

Page 6

DC Electrical Characteristics Symbol Parameter I Quiescent Supply Current CC I Increase in I per Input CC CC Note 6: Outputs disabled or 3-STATE only. AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PHL t ...

Page 7

AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C t PLH t PZL t PZH Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable and Disable Times for Logic (Input Characteristics; ...

Page 8

Schematic Diagram Generic for LCX Family www.fairchildsemi.com 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

Related keywords