IS62LV256L-15J Integrated Silicon Solution, IS62LV256L-15J Datasheet

IS62LV256L-15J

Manufacturer Part Number

IS62LV256L-15J

Description

Manufacturer

Integrated Silicon Solution

Datasheets

1.IS62LV256L-15J.pdf (8 pages)

2.IS62LV256L-15J.pdf (7 pages)

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FEATURES

• High-speed access time: 15, 20, 25 ns

• Automatic power-down when chip is deselected

• CMOS low power operation

• TTL compatible interface levels

• Single 3.3V power supply

• Fully static operation: no clock or refresh

• Three-state outputs

Integrated Circuit Solution Inc.

SR007-0B

IS62LV256L

32K x 8 LOW VOLTAGE

CMOS STATIC RAM

— 255 mW (max.) operating

— 0.18 mW (max.) CMOS standby

required

FUNCTIONAL BLOCK DIAGRAM

I/O0-I/O7

A0-A14

GND

VCC

DECODER

CIRCUIT

CONTROL

CIRCUIT

DATA

I/O

DESCRIPTION

The

32,768-word by 8-bit static RAM. It is fabricated using

high-performance CMOS technology. This highly reliable pro-

cess coupled with innovative circuit design techniques, yields

access times as fast as 15 ns maximum.

When CE is HIGH (deselected), the device assumes a standby

mode at which the power dissipation is reduced to

50 µW (typical) with CMOS input levels.

Easy memory expansion is provided by using an active LOW

Chip Enable (CE). The active LOW Write Enable (WE) controls

both writing and reading of the memory.

The IS62LV256L is available in the JEDEC standard 28-pin

300mil SOJ and the 8*13.4mm TSOP-1 package.

ICSI

IS62LV256L is a very high-speed, low power,

MEMORY ARRAY

COLUMN I/O

256 X 1024

ICSI

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