74HCT652D,112 NXP Semiconductors, 74HCT652D,112 Datasheet - Page 2

• Manufacturer Part Number: 74HCT652D,112
• Description: IC TRANSCEIVER 8BIT INV 24SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT652D,112

• Logic Type: Transceiver, Inverting
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Current - Output High, Low: 6mA, 6mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74HCT652D; 74HCT652D; 935051240112

Philips Semiconductors
FEATURES
APPLICATIONS
DESCRIPTION
The 74HC/HCT652 are high-speed
SI-gate CMOS devices and are pin
compatible with Low power Schottky
TTL (LSTTL). They are specified in
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
September 1993
SYMBOL
t
t
t
f
C
C
PLH
PHZ
PHZ
max
Multiplexed real-time and stored
data
Independent register for A and B
buses
Independent enables for A and B
buses
3-state
Output capability: Bus driver
Low power consumption by CMOS
technology
I
Bus interfaces.
Octal bus transceiver/register; 3-state
I
PD
CC
P
f
f
For HCT the condition is V
i
o
/t
/t
/t
D
PD
= input frequency in MHz; C
category: MSI.
PZL
PZL
PLZ
= output frequency in MHz; V
(C
= C
is used to determine the dynamic power dissipation (P
L
PD
V
amb
CC
V
2
PARAMETER
propagation delay A
propagation delay CP
propagation delay S
3-state output enable time OE
3-state output disable time OE
maximum clock frequency
input capacitance
power dissipation capacitance per channel
CC
= 25 C; t
f
2
o
) = sum of the outputs
f
i
r
= t
(C
I
f
= GND to V
I
= 6 ns; V
L
= GND to V
L
V
= output load capacitance in pF;
CC
CC
n
AB
/B
AB
/S
= supply voltage in V;
2
n
/CP
CC
BA
compliance with Jedec standard
no. 7A.
The 74HC/HCT652 consist of 8
non-inverting bus transceiver circuits
with 3-state outputs, D-type flip-flops
and central circuitry arranged for
multiplexed transmission of data
directly from the data bus or from the
internal storage registers. Data on the
“A” or “B” or both buses, will be stored
in the internal registers, at the
appropriate clock pins (CP
CP
(S
and OE
on the select inputs S
can directly go from input to output
(real time mode) or data can be
controlled by the clock (storage
mode), this is when the output enable
pins this operating mode permits. The
output enable pins OE
determine the operation mode of the
transceiver. When OE
data transmission from A
to B
CC
f
AB
o
CC
= 4.5 V; C
to B
BA
BA
) where:
n
and S
) regardless of the select pins
/A
AB
AB
to B
n
1.5 V
BA
n
/OE
/A
/OE
) control pins. Depending
n
n
BA
/A
BA
BA
L
) or output enable (OE
n
= 50 pF.
to B
to B
2
n
n
/A
/A
AB
n
n
AB
D
AB
and S
in W):
is LOW, no
n
and OE
to B
AB
or
BA
n
is
data
BA
CONDITIONS
C
V
notes 1 and 2
CC
AB
L
= 15 pF;
= 5 V
possible and when OE
there is no data transmission from B
to A
in the real time transfer mode, it is
also possible to store data without
using the internal D-type flip-flops by
simultaneously enabling OE
OE
output reinforces its input. Thus when
all other data sources to the two sets
of bus lines are at high-impedance,
each set of the bus lines will remain at
its last state. This type differs from the
HC/HCT646 in one extra
bus-management function. This is the
possibility to transfer stored “A data to
the “B” bus and transfer stored ”B”
data to the ”A” bus at the same time.
The examples at the application
information demonstrate all bus
management functions.
Schmitt-trigger action in the clock
inputs makes the circuit highly
tolerant to slower clock rise and fall
times.
BA
n
possible. When S
. In this configuration each
HC
13
18
20
14
12
92
3.5
26
74HC/HCT652
TYPICAL
Product specification
HCT
13
20
23
15
13
92
3.5
28
AB
BA
and S
is HIGH,
AB
UNIT
ns
ns
ns
ns
ns
MHz
pF
pF
and
BA
are
n