M25PE10 Numonyx, B.V., M25PE10 Datasheet - Page 8

• Manufacturer Part Number: M25PE10
• Description: 1 and 2 Mbit, page-erasable serial Flash memories with byte alterability, 75 MHz SPI bus, standard pinout
• Manufacturer: Numonyx, B.V.

Signal descriptions
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Signal descriptions
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data output (Q) is at high
impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the
device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving
Chip Select (S) Low selects the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
Reset (Reset)
The Reset (Reset) input provides a hardware reset for the memory.
When Reset (Reset) is driven High, the memory is in the normal operating mode. When
Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output
is high impedance.
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation
(write, program or erase cycle) and data may be lost.
Top Sector Lock (TSL)
This input signal puts the device in the Hardware Protected mode, when Top Sector Lock
(TSL) is connected to V
become read-only (protected from write, program and erase operations).
When Top Sector Lock (TSL) is connected to V
the other pages of memory.
SS
, causing the top 256 pages (upper addresses) of the memory to
CC
, the top 256 pages of memory behave like
M25PE20, M25PE10