M25P32 Numonyx, B.V., M25P32 Datasheet
M25P32
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M25P32 Summary of contents
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... More than 20 year data retention ■ Packages – ECOPACK® (RoHS compliant) December 2007 32-Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface = 9 V) Rev 11 M25P32 VDFPN8 (ME) 8 × (MLP8) VFQFPN8 (MP) 6 × SO16 (MF) 300 mils width SO8W (MW) 208 mils www ...
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... Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13 4.4 Fast Program/Erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 13 4.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 2/53 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 M25P32 ) . . . . . . . . . . . . 10 PP ...
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... M25P32 6.4.2 6.4.3 6.4.4 6.5 Write Status Register (WRSR 6.6 Read Data Bytes (READ 6.7 Read Data Bytes at Higher Speed (FAST_READ 6.8 Page Program (PP 6.9 Sector Erase (SE 6.10 Bulk Erase (BE 6.11 Deep Power-down (DP 6.12 Release from Deep Power-down and Read Electronic Signature (RES Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 Maximum rating ...
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... SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, mechanical data Table 17. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 18. SO8W 8 lead Plastic Small Outline, 208 mils body width, package mechanical data Table 19. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4/53 M25P32 ...
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... M25P32 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10 ...
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... Description 1 Description The M25P32 Mbit ( Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. An enhanced Fast Program/Erase mode is available to speed up operations in factory environment ...
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... M25P32 W/V PP HOLD V SS Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect/Enhanced Program supply voltage Hold Supply voltage Ground M25P32 W section for package dimensions, and how to identify pin-1. Description Q AI07483b ...
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... Description Figure 3. SO connections Don’t Use 2. See Package mechanical 8/53 M25P32 HOLD section for package dimensions, and how to identify pin-1. M25P32 W/V PP AI07484c ...
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... M25P32 2 Signal description 2.1 Serial data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.2 Serial data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C) ...
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... stable until the Program/Erase algorithm is completed. 2.7 V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS 10/53 it acts as an additional power supply pin. In this case V PPH supply voltage. CC M25P32 ) PP ) the pin is seen as a control CC must PP ...
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... Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25P32 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance ...
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... R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 5. SPI modes supported CPOL CPHA 12/ µs <=> the application must ensure that the Bus p MSB M25P32 MSB AI01438B ...
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... M25P32 4 Operating features 4.1 Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration t To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory ...
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... Protection modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P32 features the following data protection mechanisms: ● Power On Reset and an internal timer (t changes while the power supply is outside the operating specification. ...
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... M25P32 Table 2. Protected area sizes Status Register content BP2 BP1 BP0 bit bit bit The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are ...
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... Operating features Figure 6. Hold condition activation C HOLD 16/53 Hold Condition (standard use) M25P32 Hold Condition (non-standard use) AI02029D ...
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... M25P32 5 Memory organization The memory is organized as: ● 4,194,304 bytes (8 bits each) ● 64 sectors (512 Kbits, 65536 bytes each) ● 16384 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. ...
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... M25P32 3FFFFFh 3EFFFFh 3DFFFFh 3CFFFFh 3BFFFFh 3AFFFFh 39FFFFh 38FFFFh 37FFFFh 36FFFFh 35FFFFh 34FFFFh 33FFFFh 32FFFFh 31FFFFh 30FFFFh 2FFFFFh 2EFFFFh 2DFFFFh 2CFFFFh ...
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... M25P32 Table 3. Memory organization (continued) Sector Address range 1C0000h 1B0000h 1A0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h ...
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... Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. 20/53 Table 4. M25P32 ...
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... M25P32 Table 4. Instruction set Instruction WREN Write Enable WRDI Write Disable RDID Read Identification RDSR Read Status Register WRSR Write Status Register READ Read Data bytes Read Data bytes at higher FAST_READ speed PP Page Program SE Sector Erase BE Bulk Erase DP Deep Power-down Release from Deep Power- ...
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... Write Status Register (WRSR) instruction completion ● Page Program (PP) instruction completion ● Sector Erase (SE) instruction completion ● Bulk Erase (BE) instruction completion Figure 9. Write Disable (WRDI) instruction sequence 22/53 (Figure 9) resets the Write Enable Latch (WEL) bit Instruction D High Impedance AI03750D M25P32 ...
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... M25P32 6.3 Read Identification (RDID) The Read Identification (RDID) instruction allows to read the device identification data: ● Manufacturer identification (one byte) ● Device identification (two bytes) ● A Unique ID code (UID) followed by 16 bytes of CFI data The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. ...
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... BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0. 24/ BP2 Figure 11. BP1 BP0 WEL Block Protect bits Write Enable Latch bit Write In Progress bit Table 2) becomes M25P32 b0 WIP ...
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... M25P32 6.4.4 SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W/V ) signal. The Status Register Write Disable (SRWD) bit and Write Protect PP (W/V ) signal allow the device to be put in the Hardware Protected mode (when the Status PP Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/V ...
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... D Q 26/53 Figure 12. Table 2. The Write Status Register (WRSR) instruction also allows ) signal. The Status Register Write Disable (SRWD) bit and Write Instruction 7 High Impedance MSB Status Register AI02282D M25P32 ) is W ...
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... M25P32 Table 7. Protection modes W/V SRWD PP signal bit Protected 1 1 Hardware 0 1 Protected 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2. The protection features of the device are summarized in When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial ...
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... High Impedance Q 1. Address bits A23 to A22 are Don’t Care. 28/53 Figure 13 Instruction 24-Bit Address MSB Data Out MSB M25P32 Data Out 2 7 AI03748D ...
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... M25P32 6.7 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). ...
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... Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see 30/53 Figure 15. Table 2 and Table 3) is not executed. M25P32 ...
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... M25P32 Figure 15. Page Program (PP) instruction sequence Data Byte MSB 1. Address bits A23 to A22 are Don’t Care Instruction 24-Bit Address MSB Data Byte 3 ...
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... D 1. Address bits A23 to A22 are Don’t Care. 32/ valid address for the Sector Erase (SE) instruction. Chip Select (S) Figure 16. Table 2 and Table 3) is not executed Instruction 23 22 MSB Bit Address AI03751D M25P32 ) is ...
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... M25P32 6.10 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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... Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 18. Deep Power-down (DP) instruction sequence 34/53 Table 13). Figure 18 Instruction before the supply current is reduced Stand-by Mode Deep Power-down Mode M25P32 to CC1 AI03753D ...
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... Deep Power-down mode. The instruction can also be used to read, on Serial Data Output (Q), the old-style 8-bit Electronic Signature, whose value for the M25P32 is 15h. Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature that is read by the Read Identifier (RDID) instruction ...
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... C Instruction D High Impedance Q 1. The value of the 8-bit Electronic Signature, for the M25P32, is 15h. Figure 20. Release from Deep Power-down (RES) instruction sequence Instruction D High Impedance Q Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has been transmitted for the first time (as shown in still ensures that the device is put into Standby Power mode ...
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... M25P32 7 Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on V ● V (min) at Power-up, and then for a further delay ● Power-down SS A safe configuration is provided in To avoid data corruption and inadvertent write operations during Power-up, a Power On Reset (POR) circuit is included ...
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... PUW (1) V Write Inhibit voltage WI 1. These parameters are characterized only. 38/53 Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed tVSL tPUW threshold WI Parameter M25P32 Read Access allowed Device fully accessible time AI04009C Min. Max. Unit 1.5 2.5 µ ...
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... M25P32 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 9 Maximum rating Stressing the device outside the ratings listed in the device ...
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... Test condition V OUT =25 °C and a frequency of 20 MHz. A Min. Typ. Max. 2.7 3.6 8.5 9.5 – Min. Max 0. 0. Input and Output 0.7V CC 0.5V CC 0.3V CC AI07455 Min. Max M25P32 Unit V V °C °C Unit Unit pF pF ...
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... M25P32 Table 13. DC characteristics Symbol I Input leakage current LI I Output leakage current LO I Standby current CC1 I Deep Power-down current CC2 I Operating current (READ) CC3 I Operating current (PP) CC4 I Operating current (WRSR) CC5 I Operating current (SE) CC6 I Operating current (BE) CC7 Operating current for Fast ...
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... Table 11 (2) Min. Typ. Max. D. 0.1 0 100 100 200 30 30 M25P32 Unit MHz MHz ns ns V/ns V/ µs µs ...
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... M25P32 Table 14. AC characteristics ( Applies only to products made with T9HX technology, identified with Process digit “4” Test conditions specified in Symbol Alt. t Write Status Register cycle time W Page Program cycle time (256 bytes) (8) t Page Program cycle time (n bytes) PP Page Program cycle time (V ...
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... DC and AC parameters Figure 24. Write Protect Setup and Hold timing during WRSR when SRWD=1 W/V PP tWHSL High Impedance Q Figure 25. Hold timing HOLD 44/53 tHLCH tCHHL tCHHH tHLQZ tHHQX M25P32 tSHWL AI07439b tHHCH AI02032 ...
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... M25P32 Figure 26. Output timing S C tCLQV tCLQX Q ADDR.LSB IN D Figure 27. V PPH PPH W/V PP tCLQV tCLQX timing PP, SE, BE tVPPHSL DC and AC parameters tCH tCL LSB OUT tQLQH tQHQL End of PP (identified by WPI polling) tSHQZ AI01449e ai12092 45/53 ...
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... 46/ millimeters Typ Min Max 0.85 1.00 0.00 0.05 0.40 0.35 0.48 8.00 5.16 0.05 6.00 4.80 1.27 – – 0.82 0.50 0.45 0.60 0. ddd VDFPN-02 inches Typ Min 0.0335 0.0000 0.0157 0.0138 0.3150 0.2031 0.2362 0.1890 0.0500 – 0.0323 0.0197 0.0177 8 M25P32 Max 0.0394 0.0020 0.0189 0.0020 – 0.0236 0.0059 ...
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... M25P32 Figure 29. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, package outline SO-H 1. Drawing is not to scale. Table 16. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, mechanical data Symbol θ ddd D 16 ...
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... Typ Min Max 0.85 0.80 1.00 0.00 0.05 0.65 0.20 0.40 0.35 0.48 6.00 5.75 3.40 3.20 3.60 5.00 4.75 4.00 3.80 4.30 1.27 – – 0.60 0.50 0.75 12° VFQFPN-01 inches Typ Min 0.0335 0.0315 0.0000 0.0256 0.0079 0.0157 0.0138 0.2362 0.2264 0.1339 0.1260 0.1969 0.1870 0.1575 0.1496 0.0500 – 0.0236 0.0197 M25P32 e b Max 0.0394 0.0020 0.0189 0.1417 0.1693 – 0.0295 12° ...
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... M25P32 Figure 31. SO8W 8 lead Plastic Small Outline, 208 mils body width, package outline 1. Drawing is not to scale. Table 18. SO8W 8 lead Plastic Small Outline, 208 mils body width, package mechanical data Symbol millimeters ...
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... Numonyx Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 50/53 M25P32 – (1) (1) M25P32 ...
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... M25P32 13 Revision history Table 20. Document revision history Date Revision 28-Apr-2003 15-May-2003 20-Jun-2003 18-Jul-2003 24-Sep-2003 04-Dec-2003 10-Dec-2003 01-Apr-2004 05-Aug-2004 01-Oct-2004 01-Apr-2005 01-Aug-2005 23-Jan-2006 10-Feb-2006 28-Nov-2006 0.1 Target Specification Document written in brief form 0.2 Target Specification Document written in full 0.3 8x6 MLP8 and SO16(300 mil) packages added ...
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... Figure 10: Read Identification (RDID) instruction sequence and data-out sequence. Modified Test condition and maximum value for I characteristics. Modified the maximum value for f technology). Table 14: AC characteristics removed. 11 Applied Numonyx branding. M25P32 Changes modified. Section 6.3: Read Identification Table 5: Read Identification Table 4: Instruction set. in Table 13: DC CC3 ...
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... M25P32 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ...