STPCC03 STMicroelectronics, STPCC03 Datasheet - Page 4

• Manufacturer Part Number: STPCC03
• Description: STPC CONSUMER-S DATASHEET- PC COMPATIBLE EMBEDDED MICROPROCESSOR
• Manufacturer: STMicroelectronics

GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
At the heart of the STPC Consumer-S is an ad-
vanced 64-bit processor block, dubbed the
5ST86. The 5ST86 includes a 5th generation
processor core along with a 64-bit SDRAM con-
troller, advanced 64-bit accelerated graphics and
video controller, a high speed PCI local-bus con-
troller and Industry standard PC chip set functions
(Interrupt controller, DMA Controller, Interval timer
and ISA bus).
The STPC Consumer-S makes use of a tightly
coupled Unified Memory Architecture (UMA),
where the same memory array is used for CPU
main memory and graphics frame-buffer. This
means a reduction in total system memory for sys-
tem performances that are equal to that of a com-
parable Frame Buffer and system memory based
system, and generally much better, due to the
higher memory bandwidth allowed by attaching
the graphics engine directly to the 64-bit proces-
sor host interface running at the speed of the proc-
essor bus rather than the traditional PCI bus.
The 64-bit wide memory array provides the sys-
tem with 528MB/s peak bandwidth. This allows for
higher resolution screens and greater color depth.
The ‘standard’ PC chipset functions (DMA, inter-
rupt controller, timers, power management logic)
are integrated together with the x86 processor
core; additional functions such as communica-
tions ports are accessed by the STPC Consumer-
S via internal ISA bus.
The PCI bus is the main data communication link
to the STPC Consumer-S chip. The STPC Con-
sumer-S translates appropriate host bus I/O and
Memory cycles onto the PCI bus. It also supports
generation of Configuration cycles on the PCI bus.
The STPC Consumer-S, as a PCI bus agent (host
bridge class), fully complies with PCI specification
2.1. The chip-set also implements the PCI manda-
tory header registers in Type 0 PCI configuration
space for easy porting of PCI aware system BI-
OS. The device contains a PCI arbitration function
for three external PCI devices.
The STPC Consumer-S has two functionnal
blocks sharing the same balls : The ISA / IPC /
IDE block and the Local Bus / IDE block (seeTa-
ble 2-1 & Table 2-4). Any board with the STPC
Consumer-S should be built using only one of
these two configurations.
At reset, the configuration is done by ‘strap op-
tions’ which initialises the STPC Consumer-S to
the right settings. It is a set of pull-up or pull-down
4/59
Issue 1.1 - October 16, 2000
resistors on the memory data bus, checked on re-
set, which auto-configure the STPC Consumer-S.
GRAPHICS FUNCTIONS
Graphics functions are controlled through the on-
chip SVGA controller and the monitor display is
produced through the 2D graphics display engine.
This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics drawing operations which include hard-
ware acceleration of text, bitblts, transparent blts
and fills. The results of these operations change
the contents of the on-screen or off-screen Frame
Buffer areas of DRAM memory. The Frame Buffer
can occupy a space up to 4 Mbytes anywhere in
the physical main memory and always starts from
the bottom of the main physical memory.
The graphics resolution supported is a maximum
of 1280x1024 in 65536 colours and 1024x768 in
true color at 75Hz refresh rate and is VGA and
SVGA compatible. Horizontal timing fields are
VGA compatible while the vertical fields are ex-
tended by one bit to accommodate above display
resolution.
VIDEO FUNCTIONS
The STPC Consumer-S provides several addition-
al functions to handle MPEG or similar video
streams. The Video Input Port accepts an encod-
ed digital video stream in one of a number of in-
dustry standard formats, decodes it, optionally
decimates it, and deposits it into an off screen
area of the Frame Buffer. An interrupt request can
be generated when an entire field or frame has
been captured. The video output pipeline incorpo-
rates a video-scaler and color space converter
function and provisions in the CRT controller to
display a video window. While repainting the
screen the CRT controller fetches both the video
as well as the normal non-video Frame Buffer in
two separate internal FIFOs. The video stream
can be color-space converted (optionally) and
smooth scaled. Smooth interpolative scaling in
both horizontal and vertical direction are imple-
mented. Color and Chroma key functions are also
implemented to allow mixing video stream with
non-video Frame Buffer.
The video output passes directly to the RAMDAC
for monitor output or through another optional
color space converter (RGB to 4:2:2 YCrCb) to the
programmable anti-flicker filter. The flicker filter is