STPCI2 STMicroelectronics, STPCI2 Datasheet - Page 27

• Manufacturer Part Number: STPCI2
• Description: STPC ATLAS DATASHEET - X86 CORE PC COMPATIBLE SYS
• Manufacturer: STMicroelectronics

BASIC CLOCKS AND RESETS
XTALO
ISA_CLK
ISA_CLK2X
OSC14M
DEV_CLK
HCLK
PCI_CLKO
DCLK
MEMORY CONTROLLER
MCLKO
CS#[3:1]
CS#[0]
MA[10:0], BA[0]
RAS#[1:0], CAS#[1:0]
MWE#, DQM[7:0]
MD[63:0]
PCI INTERFACE
AD[31:0]
CBE[3:0], PAR
FRAME#, TRDY#, IRDY#
STOP#, DEVSEL#
PERR#, SERR#
PCI_GNT#[2:0]
ISA BUS INTERFACE
ISAOE#
RMRTCCS#
LA[23:17]
SA[19:0]
SD[15:0]
BHE#, MEMR#
MEMW#, SMEMR#, SMEMW#, IOR#, IOW# Unknown
REF#
ALE, AEN
DACK_ENC[2:0]
TC
GPIOCS#
RTCDS#, RTCRW#, KBCS#
RTCAS
PCMCIA INTERFACE
RESET
A[23:0]
D[15:0]
IORD#, IOWR#, OE#
WE#, REG#
CE2#, CE1#, VCC5_EN, VCC3_EN
VPP_PGM, VPP_VCC
LOCAL BUS INTERFACE
PA[24:0]
PD[15:0]
PRD#
PBE#[1:0], FCS0#, FCS_0H#
Signal Name
Table 2-5. Signal value on Reset
14MHz
Low
14MHz
14MHz
24MHz
Oscillating at the speed defined by the strap options.
HCLK divided by 2 or 3, depending on the strap options.
17MHz
66MHz if asynchonous mode, HCLK speed if synchronized mode.
High
High
0x00
High
High
Input
0x0000
Low
Input
Input
Input
High
High
Hi-Z
Unknown
0xFFFXX
Unknown
Unknown
Unknown
Low
Input
Input
Hi-Z
Hi-Z
Unknown
Unknown
Unknown
Unknown
Unknown
High
High
Low
Unknown
Unknown
Unknown
High
Issue 1.0 - July 24, 2002
SYSRSTI# active
7MHz
0x00
0xFFF03
0xFF
High
High
High
Low
High
0x00
0xFF
High
0xFF
High
SYSRSTI# inactive
SYSRSTO# active
SDRAM init sequence:
Write Cycles
First prefetch cycles
when not in Local Bus mode.
Low
First prefetch cycles
when in ISA or PCMCIA mode.
Address start is 0xFFFFF0
0x04
Low
High
First prefetch cycles
using RMRTCCS#
First prefetch cycles
release of SYSRSTO#
PIN DESCRIPTION
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