MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 24

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Communications Processor Module (CPM) Ports
1-20
General-
Purpose
PA28
PA27
PA26
I/O
FCC1: RXENB
UTOPIA master
FCC1: RXENB
UTOPIA slave
FCC1: TX_EN
MII
FCC1: RXSOC
UTOPIA slave
FCC1: RX_DV
MII
FCC1: RXCLAV
UTOPIA slave
FCC1: RXCLAV
UTOPIA master, or
RXCLAV0
UTOPIA master, Multi-PHY,
direct polling
FCC1: RX_ER
MII
Peripheral Controller:
Name
Dedicated Signal
Protocol
Table 1-3. Port A Signals (Continued)
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Input
Input
Input
Input
Input
FCC1: UTOPIA Master Receive Enable
In the ATM UTOPIA interface supported by FCC1. (UTOPIA
master) RXENB is asserted by the MSC8103 (UTOPIA
master PHY) to indicate that RXD[0–7] and RXSOC are to
be sampled at the end of the next cycle. RXD[0–7] and
RXSOC are enabled only in cycles following those with
RXENB asserted.
FCC1: UTOPIA Master Receive Enable
In the ATM UTOPIA interface supported by FCC1. (UTOPIA
slave) RXENB is an input asserted by an external PHY to
indicate that RXD[0–7] and RXSOC is to be sampled at the
end of the next cycle. RXD[0–7] and RXSOC are enabled
only in cycles following those with RXENB asserted.
FCC1: Media Independent Interface Transmit Enable
In the MII interface supported by FCC1. TX_EN is asserted
by the MSC8103 when transmitting data.
FCC1: UTOPIA Receive Start of Cell
Asserted by the MSC8103 (UTOPIA slave) for an external
PHY when RXD[0–7] contains the first valid byte of the cell.
FCC1: Media Independent Interface Receive Data Valid
In the MII interface supported by FCC1. RX_DV is an input
asserted by an external fast Ethernet PHY. RX_DV
indicates that valid data is being sent. The presence of
carrier sense but not RX_DV indicates reception of broken
packet headers, probably due to bad wiring or a bad circuit.
FCC1: UTOPIA Slave Receive Cell Available
In the ATM UTOPIA interface supported by FCC1. RXCLAV
is asserted by the MSC8103 (UTOPIA slave PHY) when
one complete ATM cell is available for transfer.
FCC1: UTOPIA Master Receive Cell Available
In the ATM UTOPIA interface supported by FCC1. RXCLAV
is asserted by an external PHY when one complete ATM
cell is available for transfer.
FCC1: UTOPIA Master Receive Cell Available 0 Direct
Polling
In the ATM UTOPIA interface supported by FCC1,
RXCLAV0 is asserted by an external PHY when one
complete ATM cell is available for transfer.
FCC1: Media Independent Interface Receive Error
In the MII interface and supported by FCC1. RX_ER is
asserted by an external fast Ethernet PHY. This signal
indicates a receive error, which often indicates bad wiring.
Description