MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 72

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MSC8103M1100

Manufacturer Part Number
MSC8103M1100
Description
Network Processor, Networking Digital Signal Processor
Manufacturer
Motorola / Freescale Semiconductor
Datasheet

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AC Timings
2.7.5 CPM Timings
2-22
Figure 2-13 shows Host DMA write timing.
Note:
No.
16
17
18
19
20
21
22
23
FCC input setup time before low-to-high clock transition
FCC input hold time after low-to-high clock transition
SCC/SMC/SPI/I
SCC/SMC/SPI/I
TDM input setup time before low-to-high serial clock transition
TDM input hold time after low-to-high serial transition
PIO/TIMER/DMA input setup time before low-to-high serial clock transition
PIO/TIMER/DMA input hold time after low-to-high serial clock transition
FCC, SCC, SMC, SPI, I
a. internal clock (BRGxO)
b. external clock (serial clock input)
a. internal clock (BRGxO)
b. external clock (serial clock input)
a. internal clock (BRGxO)
b. external clock (serial clock input)
a. internal clock (BRGxO)
b. external clock (serial clock input)
2
2
C input setup time before low-to-high clock transition
C input hold time after low-to-high clock transition
HRD (Input)
HWR, HDS,
Figure 2-13. Host DMA Write Timing Diagram
HD[0–15]
HACK or
(Output)
(Output)
HREQ
Table 2-19. CPM Input Characteristics
2
C are Non-Multiplexed Serial Interface signals.
Characteristic
64
TX[0–3]
47
Write
45
Valid
Data
46
63
48
Typical
10
20
20
20
10
5
0
3
5
0
5
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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