MSAN-107 Zarlink Semiconductor, Inc., MSAN-107 Datasheet - Page 2

• Manufacturer Part Number: MSAN-107
• Description: Understanding and Eliminating Latch-Up in CMOS Applications
• Manufacturer: Zarlink Semiconductor, Inc.

MSAN-107
Semiconductor Device Considerations
Background on SCR’s
Prior to discussing latch-up in CMOS devices, it is
advantageous to briefly review the basic theory of
SCR operation. This will be helpful in developing an
understanding of the relationships between external
circuit and system conditions and the resultant
triggerng of latch-up in CMOS devices. The basic
SCR structure is that of a four-layer device as shown
in Fig. 1. The device has three terminals: Anode,
Cathode and Gate. Fig. 2 shows how the SCR can
be modelled with two bipolar transistors, one NPN
and one PNP. In the normal mode of operation, the
SCR is turned on by injecting sufficient current into
the base of Q
done, Q
base-emitter junction of Q
turns on, injecting additional current into Q
This in turn causes Q
more base current to Q
arrangement sustains conduction, and ensures that
the SCR continues to conduct even if the gate
current is interrupted.
The device will remain in this latched state
indefinitely. To turn the SCR off, one of two things
can be done. If the voltage applied across the SCR
is reduced to the point where Q
junction turns off (V
base current and the SCR will turn off. Alternatively,
if the current through the SCR is reduced below its
holding current then it will also turn off. The holding
current is the minimum current required to sustain
conduction and is a function of the physical
dimensions of the device and the transistor gains
(Fig. 3). As mentioned, this is the way that the SCR
A-32
2
Figure 2 - Bipolar Model of an SCR
begins to draw collector current via the
2
to turn this transistor on. When this is
Sus
2
), then Q
to turn on harder, supplying
1
.
1
.
This positive feedback
As a result Q
2
will be starved of
1
’s base-emitter
2
’s base.
1
also
is controlled in normal applications.
various other ways that an SCR may be triggered.
These must be examined as they are directly related
to latch-up problems.
Looking at Fig. 2, it can be seen that the load current
and the two emitter currents of Q
equal. Also the load current is equal to the sums of
the two collector currents and a leakage current from
Q
(refer to Appendix) that:
Where B
respectively.
Normally, with no base current supplied to Q
load current will be small since the leakage I
small, as are the current gains (B
value of collector current. If however, the current
gains increase to the point where the product, B
B
become very large, limited only by the load
impedance, the series impedance of the SCR, and
source impedance of the power supply.There are
various applied conditions that will cause this to
happen.
breakover voltage, V
anode-cathode voltage across the SCR increases,
the collector-emitter voltages of Q
increase.
collector-base reverse biases.
junctions of the two transistors are physically the
same area, the N
Figure 3 - SCR Current-Voltage Characteristic
2
2
, approaches unity, then the load current will
I
’s collector to its base (I
L
= I
CBO
1
and B
Increasing the load voltage beyond the
This corresponds to increases in the
2
2
are the current gains of Q
1
-P
BO
(1 + B
2
, will have this effect. As the
(1 - B
junction (Fig. 1).
CBO2
1
)(1 + B
Application Note
1
B
). It can be shown
The collector-base
2
)
1
1
, B
1
and Q
2
)
2
and Q
) at this low
There are
1
2
CBO2
and Q
As the
are all
2
2
, the
also
(1)
is
2
1