MSAN-107 Zarlink Semiconductor, Inc., MSAN-107 Datasheet - Page 3

• Manufacturer Part Number: MSAN-107
• Description: Understanding and Eliminating Latch-Up in CMOS Applications
• Manufacturer: Zarlink Semiconductor, Inc.

Application Note
reverse bias increases, the energy of the minority
carriers increases causing more carriers to be
dislodged, which in turn pick up energy.
continues until the junction undergoes an avalanche
breakdown resulting in an increase in the collector
currents of Q
and B
A very rapid change in the anode to cathode voltage
of an SCR can also cause it to trigger. This is known
as the “dV/dt” effect.
reversed biased, exhibits a capacitance.
capacitance varies with the reverse bias voltage
applied across the junction.
through the capacitor is described by:
The
increasing reverse bias and hence the second term
of equation (3) is negative. If, however, the rate of
change of applied voltage is large enough, the first
term of equation (3) will dominate and the current
through the SCR will increase.
increases sufficiently to cause the B
approach unity, then the SCR will latch on.
The effects of temperature must also be noted at this
point. Increasing temperature will cause an increase
in both the leakage current through the SCR and in
the current gains B
As such, the magnitude of the driving force required
to turn the SCR on will decrease with increasing
temperature. In other words, the SCR will be more
easily triggered as temperature increases for any of
the triggering mechanisms described.
Corollaries exist between each of the three methods
of turning an SCR on as described, and the ways in
which the parasitic SCR structures of CMOS devices
are triggered.
SCR is by injecting current into its gate terminal.
This corresponds to forcing current into the inputs or
outputs of a CMOS device by applying voltages that
go outside of the power supply rails. This is by far
the most common form of latch-up triggering. The
avalanche breakdown mechanism described also
applies directly to CMOS devices, although its
occurrence is far less prevelant. Excessive voltage
on the power supply pins, whether continuous or
transient, may result in latch-up occurrence.
also theoretically possible to trigger parasitic SCR
devices by the dV/dt method as a result of high
speed transients on the supply rails. However, this
will rarely happen in a real application.
2
junction
cause the SCR to latch on.
=
1
d(C
C
and Q
j
dV
capacitance,
The normal mode of triggering an
dt
dt
j
V
1
AK
AK
B
2
2
. The resulting increase in B
)
of the two bipolar transistors.
The N
+
V
AK
C
1
dt
-P
Hence the current
j
dC
2
decreases
j
junction, being
1
If the current
B
2
product to
Each of
(2)
(3)
This
This
with
It is
1
these triggering methods will be examined in the
next section in the context of the ISO-CMOS
topology for both the output and input structures.
Parasitic Bipolar Structures in the ISO-CMOS
Topology
As with any CMOS technology, ISO-CMOS contains
certain parasitic bipolar structures associated with its
output devices and input protection circuitry. These
parasitic transistors are interconnected in such a way
as to form four-layer devices. As such, SCR devices
are present at both the inputs and outputs of
ISO-CMOS circuits. These devices are normally in
their off state and will remain off as long as the
absolute maximum ratings of the devices are not
exceeded.
Output SCR Structures
A typical ISO-CMOS output driver contains one
N-channel MOSFET with its source tied to V
one P-channel MOSFET with its source tied to V
The drains of the two transistors are connected
together to form the output and the gates are
commoned to form the input (Fig. 4). The fabrication
of these transistors in close proximity results in the
formation of a parasitic SCR connected directly
across the power supply rails. When triggered, this
SCR presents a low impedance to the power supply
causing excessive current to flow. This situation is
potentially destructive, resulting in damage to bond
wires or metal supply tracks on the die due to
localized overheating.
follows. A vertical NPN transistor results from the
fabrication of the N-channel device.
substrate serves as the collector and is biased at
V
and drain N- diffusions are the emitters of the
transistor. One emitter is tied to V
the output. A wide base lateral PNP transistor is
formed when a P-channel device is located close to
a N-channel transistor. The P-channel source and
DD
. The P- well acts as the base and the source
INPUT
Figure 4 - Typical Output Circuit
The SCR is formed as
V
DD
V
MSAN-107
SS
SS
and the other to
OUTPUT
The N-
SS
and
A-33
DD
.