MSAN-141 Zarlink Semiconductor, Inc., MSAN-141 Datasheet - Page 19

• Manufacturer Part Number: MSAN-141
• Description: Implementation Details of the MT8930B-31B S-T Interface
• Manufacturer: Zarlink Semiconductor, Inc.

Application Note
minimum threshold set to 16 dB below nominal pulse
amplitude. This minimum threshold on the input
circuit is required to maintain the active region of the
input signal well above the noise and crosstalk
levels.
5.3
The SNIC has self-contained clock recovery using an
on chip analog phase-locked loop. Incorporated in
the Phase-Locked Loop (PLL) is a voltage controlled
oscillator which allows the SNIC to function without
an external crystal. The PLL has both a phase and
frequency detection circuit which accelerates phase
acquisition. The extracted clock is presented on the
PLL and Jitter
1: 2
V
Bias
V=100%
LRx
SNIC
50%
7%
0%
Lowpass
Filter
5%
5%
10%
10%
Figure 20 - Transmitter Output Pulse Template
Figure 21 - Receiver Circuit
Highpass
Filter
10%
(5.21 + 1.04)
(5.21 + 5.21)
(5.21 - 1.04)
(5.21 - 0.52)
5.73 s
10.42 s
C4b pin with a nominal frequency of 4.096 MHz. If
the TE mode of the MT8930B is selected by tying pin
CK/NT low, then the frequency of the VCO will
deviate from its nominal value in the absence of a
line signal. For TE applications requiring a stable and
constant VCO frequency at all times, the CK/NT pin
of the MT8930B should be connected to a 4.096
MHz clock. This clock input will still configure the
device in TE mode while serving to train the PLL in
the absence of a line signal on the S/T bus. Note that
the MT8931B, on the other hand, requires a clock
input or a crystal to be connected to pin XTAL1/NT in
order to select TE mode. Therefore, the VCO
frequency is always centered at the proper value.
Under all conditions the TE will phase-lock to the
INFO2 signal within 50 ms. An inherent advantage of
4.17 s
5.21 s
4.69 s
6.25 s
Negative
Detector
Detector
Positive
Peak
Peak
Recovery
Circuit
Data
Nominal Pulse
MSAN-141
RNeg
RPos
A-219