T8531-TL-DB Agere Systems, Inc., T8531-TL-DB Datasheet - Page 42

• Manufacturer Part Number: T8531-TL-DB
• Description: Multichannel programmable codec chip set. Dry pack tray.
• Manufacturer: Agere Systems, Inc.

Codec Chip Set
Applications
Figure 11 shows a full line card implementation using
the T8531/T8532 codec and the L7585 SLIC with inte-
grated relays. One T8531 and two T8532 devices sup-
port 16 SLIC devices (only one L7585 SLIC is
illustrated). Figure 11 portrays only the transmission
paths inside the L7585 SLIC. L7585 functionality
includes eight solid-state relays, performing ring, test,
and break functions, a ring-trip detector, quiet polarity
reversal, 14 operating states, and more. For complete
functionality of this SLIC, refer to the L7585 data sheet.
The analog connection between the SLIC and the
codec is direct; no external components are required.
The transfer of control data on the octal interface
between the T8531 and T8532 devices is also direct.
* Optional for quiet reverse battery.
† 4.096 MHz operation; for 2.048 MHz operation, tie SCKSEL to V
42
42
RINGING
RING
TIP
82.5
82.5
TEST-IN
RPR
RPT
+5 V
BUS
BUS
CLOCK
1 MHz
(SEE BELOW)
PROTECTOR
RRTF
400
1 M
RS1*
SURGE
RELAY
260 V
K1
CVD
0.1 F
CRTF
0.1 F
50 V
BATTERY BACK
PARALLEL DATA BUS TO MICROPROCESSOR
EARTH BACK
+10 V
DGND
VCCD
RDO
TRNG
RRNG
RSW
RTS
PR
PT
RTI
TTI
CLK
VSP VBAT BGND VCCA AGND
NDET NCS B5 B4 B3 B2 B1 B0
RINGING
RINGING
–48 V
0.1 F
100 V
CVB
SLIC 0
L7585
Figure 11. Line Card Solution Using the L7585 SLIC
+5 V
0.1 F
CVA
10 V
2.4 V
DCOUT
IPROG
TRNG
RRNG
TRNG
RRNG
RCVN
RCVP
LCTH
VRTX
VITR
DCR
CF1
CF2
VTX
FB1
FB2
ITR
TXI
RPROG 64.9 k
RLCTH 24.9 k
FB1*
0.047 F
100 V
8.25 k
RGX1
CF1
0.22 F
100 V
CHANNELS
CHANNELS
CHANNEL
0.1 F
100 V
CF2
8—15
1—7
CB1
0.1 F
100 V
FB2*
0.047 F
100 V
0
SS
VRTX0
VRN0
VRP0
VTX0
0.1 F
.
0.1 F
VDDD
+5 V
+5 V
Data is synchronous with OSCK and transmits at a
4.096 MHz rate. The microprocessor control interface
is a standard 4-wire serial port connection, micropro-
cessor clock (UPCK), chip select (UPCS), data input
(UPDI), and output (UPDO). The T8531 generates a
16 MHz clock for microprocessor use. This clock is
always present. The PCM interface consists of a
system clock (SCK) input of either 2.048 MHz or
4.096 MHz, an 8 kHz system frame sync (SFS) input,
a system data transmit port (DX), and a system data
receive (DR) port. The only external components
required by the codec chip set are the power supply
decoupling. Decouple as many power supply pins as
possible; at a minimum, use one capacitor per device
side.
TEST
TEST
CODEC 0
CODEC 1
T8532
T8532
+5 V
+5 V
RSTB
RSTB
0.1 F
0.1 F
RSTB
OSFS
OSCK
OSDR0
OSDR1
OSDX0
OSDX1
CCS0
CDI
CDO
CDI
CDO
OSFS
OSCK
CCS1
OSDR2
OSDR3
OSDX2
OSDX3
INTERFACE
OCTAL
OSDR2
OSDR3
OSDX2
OSDX3
OSDR0
OSDR1
OSDX0
OSDX1
CCS1
OSCK
OSFS
CCS0
CDO
CDI
VSS
0.1 F
VDD
Lucent Technologies Inc.
T8531
ASIC
DSP
+5 V
November 2000
SCKSEL
UPCK
UPCS
UPDI
UPDO
CK16
SCK
SFS
SDR
SDX
STSXB
RSTB
INTERFACE
INTERFACE
CONTROL
PCM
†
RSTB
PROCESSOR
MICRO-
12-3351J(F)
PCM
BUS