MCC501RX166TD0B Motorola / Freescale Semiconductor, MCC501RX166TD0B Datasheet - Page 42

• Manufacturer Part Number: MCC501RX166TD0B
• Description: Network Processor, 16 Processing Elements, 166MHz Core Operating Frequency, 5Gbps Max Throughput, 838-CBGA
• Manufacturer: Motorola / Freescale Semiconductor

42
Table 21 BMU SDRAM Interface Signals
January 21, 2002— Preliminary Version
Signal Name
MD0 - MD129
MDECC0 - MDECC8 G16, F15, F14, E14, D15, D14, C14,
MA0 - MA11
MBA0 - MBA1
MCLK
MCASX
BMU SDRAM Interface
C
HAPTER
2: S
IGNAL
Pin #
R29, Q28, P28, S28, R28, P29, R27,
Q26, P26, S26, R26, P27, R25, Q24,
P24, S24, R24, P25, S22, R23, R22,
N29, M28, L28, J29, O28, N28, L29,
K28, N27, M26, L26, J28, O26, N26,
L27, K26, N25, M24, L24, J27, O24,
N24, L25, K24, P22, M22, K22, J23,
Q22, N23, L22, J25, O22, L23, J26,
J22, P23, N22, L21, J24, B29, D29,
F29, A28, C28, E28, G28, B28, D28,
F28, B27, D27, F27, A26, C26, E26,
B26, D26, F26, G26, B25, D25, F25,
A24, C24, E24, B24, D24, F24, B23,
D23, F23, G24, A22, C22, E22, B22,
D22, F22, B21, D21, F21, A20, C20,
E20, G22, B20, D20, F20, B19, D19,
F19, A18, C18, E18, B18, D18, F18,
G20, B17, D17, F17, A16, C16, E16,
B16, D16, F16, B15
B14, A14
H22, I22, H23, H24, I24, H25, H26,
I26, H27, H28, I28, H29
G18, H19
I16
J21
Signals
D
ESCRIPTIONS
The BMU and SDRAM interface signals are described in
The BMU is designed to support SDRAM devices with 12 address lines. All 139 data lines
and all 12 address lines must be connected to the SDRAM in order for the BMU to be able
to read and write external SDRAM properly.
Total Type
130
9
12
2
1
1
LVTTL
LVTTL
LVTTL
LVTTL
nc
LVTTL
I/O
I/O
I/O
O
O
nc
O
Signal Description
Data Lines In
Stored as data, ECC bits
Address Outputs: A0-A11 are sampled during the
ACTIVE command and READ/WRITE to select one
location out of the memory array in the respective
bank. The address inputs also provide the
op-code during a LOAD MODE REGISTER
command
Bank Address Outputs: BA0 and BA1 define which
bank the ACTIVE, READ, WRITE or PRECHARGE
command is being applied
Reserved
Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered.
NOTE:
code.
MCSX is considered part of the command
Table 21
.
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