A43L0616V-8 AMIC Technology, Corp., A43L0616V-8 Datasheet - Page 26

• Manufacturer Part Number: A43L0616V-8
• Description: 512K x 16 Bit x 2 Banks Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

(CL = 2)
(CL = 3)
CLOCK
Read & Write Cycle at Same Bank @Burst Length=4
(October, 1999, Version 0.0)
A10/AP
ADDR
CKE
RAS
CAS
DQ
DQM
CS
DQ
BA
WE
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
0
Row Active
(A-Bank)
Ra
Ra
1
2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row
3. Access time from Row address. t
4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)
enters precharge. Last valid output will be Hi-Z after t
At Full page bit burst, burst is wrap-around.
2
t
RCD
*Note 3
*Note 3
t
RAC
3
t
(A-Bank)
RAC
Ca0
Read
4
t
SAC
5
t
SAC
t
OH
Qa0
t
RC
6
t
*Note 1
OH
CC
Qa1
Qa0
*(t
7
RCD
Precharge
(A-Bank)
Qa2
Qa1
+ CAS latency-1) + t
8
*Note 2
t
SHZ
Qa3
Qa2
9
t
SHZ
25
High
SHZ
Qa3
*Note 4
from the clock.
10
Row Active
(A-Bank)
Rb
Rb
*Note 4
SAC
11
12
13
(A-Bank)
Db0
Db0
Write
Cb0
14
Db1
Db1
AMIC Technology, Inc.
15
Db2
Db2
16
t
t
RDL
RDL
Db3
Db3
17
Precharge
(A-Bank)
A43L0616
: Don't care
18
19