CS6100 Amphion Semiconductor Ltd., CS6100 Datasheet - Page 11

• Manufacturer Part Number: CS6100
• Description: Motion JPEG Encoder
• Manufacturer: Amphion Semiconductor Ltd.

Most inputs and outputs to the CS6100 are registered and fully synchronous. Full pin descriptions and conditional timing
behavior for non-registered pins are given in the CS6100 Databook. Example timing characteristics for the CS6100 are given in
Table 7. Timing characteristics are technology dependent and will vary by instantiation as signal loading in the target system
determines final timing.
CSO6100TK: All values reflect pre-layout estimated timing. Wireloading conditions use "Conservative" model supplied by library vendor and worst case commercial operating conditions.
Table 7: CS6100 Timing Characteristics
For applications that require the high performance, low cost and high integration of an ASIC, Amphion delivers the Optima
Cores series of multimedia ASVCs that are pre-optimized by Amphion experts to a targeted silicon technology. Choose from
off-the-shelf versions of the CSO6100 available for many popular ASIC and foundry silicon supplier technologies, or Amphion
can port the CSO6100 to a technology of your choice.
* Performance figures based on silicon vendor design kit information. ASIC performance is pre-layout using vendor-provided statistical wire loading information, under the following
** Logic gates do not include clock circuitry.
Consult your local Amphion representative for product specific performance information, current availability of individual products, and lead times on Optima core porting.
Table 8: CS6100 Optima Cores
For ASIC prototyping or for projects requiring the fast time to market of a programmable logic solution, Amphion’s Celerity
Core solutions offer the silicon-aware performance tuning found in all Amphion products, combined with the rapid design
times offered by today’s leading programmable logic solutions.
* Performance represents core only under worst case commercial conditions. Does not include timing effect of external logic and I/O circuitry.
Table 9: CS6100 Celerity Cores
conditions: (T J = 125°C, V CC -10%).
CSO6100TK
CSO6100KJ
PRODUCT ID#
PRODUCT
CSO6100
CSC6100AA
CSC6100XV
SYMBOL
t
ID#
skew
t
cyc
t
t
su
t
co
h
VENDOR
SILICON
AVAILABILITY AND IMPLEMENTATION INFORMATION
VENDOR
Amkor
SILICON
TSMC
Altera
Xilinx
Input port set-up time
Output port clock to
Input port hold time
Clock cycle rate
DESCRIPTION
output timing
Clock skew
Odyssey standard cell libraries
PROGRAMMABLE
Baseline JPEG Encoder – ASIC
LOGIC PRODUCT
Apex 20KE FPGA
0.25-micron using Synopsys
Virtex-E FPGA
0.18-micron using Artisan
standard cell libraries
NAME/PROCESS
PRODUCT
TIMING CHARACTERISTICS
CONDITION
Worst case
CELERITY
OPTIMA
(MSAMPLES/SEC)
PERFORMANCE*
max
max
max
max
40
45
™
PERFORMANCE*
(Msamples/sec)
™
CORES
CORES
VALUE
200 ps
DEVICE RESOURCES
5.5 ns
2.0 ns
0.2 ns
2.0 ns
180
140
USED (LOGIC)
4700 slices
9200 LEs
Synthesis value, final skew is design dependent
GATES**
LOGIC
JpgNext, CfgStrb, PType, RSTn at 3.0 ns
Except CLR, JpgMask AutoStart, CfgIn,
72k
73k
DEVICE RESOURCES
USED (MEMORY)
8 block RAMs
All registered outputs
17 ESB
MEMORY
0.52mm
0.85mm
COMMENT
AREA
Varies
2
2
AVAILABILITY
AVAILABILITY
Now
Now
Now
Now
Now
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