A45L9332AE-6 AMIC Technology, Corp., A45L9332AE-6 Datasheet - Page 13

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A45L9332AE-6

Manufacturer Part Number
A45L9332AE-6
Description
256K x 32 Bit x 2 Banks Synchronous Graphic RAM
Manufacturer
AMIC Technology, Corp.
Datasheet
Mode Register Filed Table to Program Modes
Register Programmed with MRS
Special Mode Register Programmed with SMRS
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 s.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
PRELIMINARY
Address
A9
Function
A8
Address
Function
0
1
0
0
1
1
A7
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256bit) is available only at Sequential mode of burst type.
4. If LC and LM both high (1), data of mask and color register will be unknown.
Write Burst Length
0
1
0
1
(Note 1)
Test Mode
Mode Register Set
A10
Single Bit
RFU
A10
Length
Burst
Vendor
(October, 2001, Version 0.1)
Type
(Note 2)
Only
Use
W.B.L
A9
A9
X
A8
A6
A8
0
0
0
0
1
1
1
1
TM
A5
0
0
1
1
0
0
1
1
CAS Latency
A7
A7
A4
A6
0
1
0
1
0
1
0
1
Load Color
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Function A5
Disable
Latency
Enable
A6
LC
A6
2
3
-
12
CAS Latency
0
1
Load Mask
A3
LM
A5
0
1
A5
Burst Type
Function
Disable
Enable
(Note 4)
Sequential
Interleave
Type
A4
A4
A2
0
0
0
0
1
1
1
1
A3
A3
BT
A1
0
0
1
1
0
0
1
1
AMIC Technology, Inc.
A45L9332A Series
A0
0
1
0
1
0
1
0
1
Burst Length
A2
A2
X
Reserved
Reserved
Reserved
256(Full)
Burst Length
BT=0
1
2
4
8
A1
A1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BT=1
(Note 3)
4
8
A0
A0

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