PM5352 PMC-Sierra, Inc., PM5352 Datasheet - Page 15

• Manufacturer Part Number: PM5352
• Description: SATURN USER NETWORK INTERFACE 155 (STAR)
• Manufacturer: PMC-Sierra, Inc.

DATA SHEET
PMC-1990421
6
6.1 Line Side Interface Signals
Pin Name
REFCLK
RXD+
RXD-
SD
RCLK
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PIN DESCRIPTION
Differential
Single-
Output
Ended
inputs
PECL
PECL
Type
Input
Input
ISSUE 2
AC5
AA1
Y2
W3
AB14
Pin
No.
Function
The reference clock input (REFCLK) must provide a
jitter-free 19.44 MHz reference clock. It is used as
the reference clock by both clock recovery and
clock synthesis circuits.
When the WAN Synchronization controller is used,
REFCLK is supplied using a VCXO. In this
application, the transmit direction can be looped
timed to any of the line receivers in order to meet
wander transfer and holdover requirements.
.
The receive differential data inputs (RXD+, RXD-)
contain the NRZ bit serial receive stream. The
receive clock is recovered from the RXD+/- bit
stream. Please refer to the Operation section for a
discussion of PECL interfacing issues.
The Signal Detect pin (SD) indicates the presence
of valid receive signal power from the Optical
Physical Medium Dependent Device. A PECL high
indicates the presence of valid data and a PECL
low indicates a loss of signal. It is mandatory that
SD be terminated into the equivalent network that
RXD+/- is terminated into.
.
The receive byte clock (RCLK) provides a timing
reference for the S/UNI-STAR receive outputs.
RCLK is a divide by eight of the recovered line rate
clock (19.44 MHz).
.
SATURN USER NETWORK INTERFACE 155 (STAR)
PM5352 S/UNI STAR
11