PM8621 PMC-Sierra, Inc., PM8621 Datasheet - Page 175

no-image

PM8621

Manufacturer Part Number
PM8621
Description
NSE-8G Standard Product Data Sheet Preliminary
Manufacturer
PMC-Sierra, Inc.
Datasheet
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
2.
3.
4.
5.
6.
7.
Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface
data bus, (D[15:0]).
A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
In non-multiplexed address/data bus architectures, ALE should be held high so parameters tS ALR ,
tH ALR , tV L , tS LR , and tH LR are not applicable.
Parameter tH AR is not applicable if address latching is used.
When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 V point of the input to the 1.4 V point of the clock.
When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds
from the 1.4 V point of the input to the 1.4 V point of the clock.
NSE-8G™ Standard Product Data Sheet
Preliminary
174

Related parts for PM8621