CD4052BMS Intersil Corporation, CD4052BMS Datasheet

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CD4052BMS

Manufacturer Part Number
CD4052BMS
Description
Rad-hard Cmos Analog Multiplexers/demultiplexers
Manufacturer
Intersil Corporation
Datasheet
December 1992
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• Logic Level Conversion
• High-Voltage Types (20V Rating)
• CD4051BMS Signal 8-Channel
• CD4052BMS Differential 4-Channel
• CD4053BMS Triple 2-Channel
• Wide Range of Digital and Analog Signal Levels:
• Low ON Resistance: 125
• High OFF Resistance: Channel Leakage of
• Logic Level Conversion:
• Matched Switch Characteristics: RON = 5
• Very Low Quiescent Power Dissipation Under All Digi-
• Binary Address Decoding on Chip
• 5V, 10V and 15V Parametric Ratings
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1 A at 18V Over Full Pack-
• Break-Before-Making Switching Eliminates Channel
Applications
• Analog and Digital Multiplexing and Demultiplexing
• A/D and D/A Conversion
• Signal Gating
* When these devices are used as demultiplexers the “CHANNEL
IN/OUT” terminals are the outputs and the “COMMON OUT/IN” ter-
minals are the inputs.
- Digital 3V to 20V
- Analog to 20Vp-p
Input Range for VDD - VEE = 15V
(typ) at VDD - VEE = 18V
- Digital Addressing Signals of 3V to 20V (VDD - VSS
- Switch Analog Signals to 20Vp-p (VDD - VEE = 20V);
VDD - VEE = 15V
tal Control Input and Supply Conditions: 0.2 W (typ)
at VDD - VSS = VDD - VEE = 10V
age Temperature Range; 100nA at 18V and +25
Overlap
= 3V to 20V)
See Introductory Text
(typ) Over 15Vp-p Signal
(typ) for
CD4051BMS, CD4052BMS
o
100pA
C
7-937
Description
CD4051BMS, CD4052BMS and CD4053BMS analog multi-
plexers/demultiplexers
switches having low ON impedance and very low OFF leak-
age current. Control of analog signals up to 20V peak-to-
peak can be achieved by digital signal amplitudes of 4.5V to
20V (if VDD-VSS = 3V, a VDD-VEE of up to 13V can be con-
trolled; for VDD-VEE level differences above 13V, a VDD-
VSS of at least 4.5V is required). For example, if VDD =
+4.5V, VSS = 0, and VEE = -13.5V, analog signals from -
13.5V to +4.5V can be controlled by digital inputs of 0 to 5V.
These multiplexer circuits dissipate extremely low quiescent
power over the full VDD-VSS and VDD-VEE supply voltage
ranges, independent of the logic state of the control signals.
When a logic “1” is present at the inhibit input terminal all
channels are off.
The CD4051BMS is a single 8 channel multiplexer having
three binary control inputs, A, B, and C, and an inhibit input.
The three binary signals select 1 of 8 channels to be turned
on, and connect one of the 8 inputs to the output.
The CD4052BMS is a differential 4 channel multiplexer hav-
ing two binary control inputs, A and B, and an inhibit input.
The two binary input signals select 1 of 4 pairs of channels
to be turned on and connect the analog inputs to the out-
puts.
The CD4053BMS is a triple 2 channel multiplexer having
three separate digital control inputs, A, B, and C, and an
inhibit input. Each control input selects one of a pair of chan-
nels which are connected in a single pole double-throw con-
figuration.
The CD4051BMS, CD4052BMS and CD4053BMS are supplied
in these 16 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4051B Only
Multiplexers/Demultiplexers*
†CD4052B, CD4053 Only
*H4X
H6W
H1E
are
CD4053BMS
digitally
CMOS Analog
†H4T
controlled
File Number
analog
3316

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CD4052BMS Summary of contents

Page 1

... The three binary signals select channels to be turned on, and connect one of the 8 inputs to the output. The CD4052BMS is a differential 4 channel multiplexer hav- ing two binary control inputs, A and B, and an inhibit input. The two binary input signals select pairs of channels ...

Page 2

... CD4051BMS, CD4052BMS, CD4053BMS Pinouts CD4051BM TOP VIEW CHANNELS IN/OUT COM OUT/ CHANNELS IN/OUT INH VEE 7 9 VSS 8 OUT/ Functional Diagrams LOGIC * LEVEL B 10 CONVERSION * INH 6 8 VSS 7 VDD Y CHANNELS IN/OUT 2 1 COMMON “Y” OUT/IN ...

Page 3

... CD4051BMS, CD4052BMS, CD4053BMS Functional Diagrams (Continued LOGIC LEVEL CONVERSION * INH 6 8 VSS 7 LOGIC LEVEL CONVERSION * INH 6 8 VSS X CHANNELS IN/OUT VDD BINARY DECODER WITH INHIBIT VEE Y CHANNELS IN/OUT CD4052BMS VDD * ALL INPUTS PROTECTED BY STANDARD CMOS PROTECTION ...

Page 4

... Specifications CD4051BMS, CD4052BMS, CD4053BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input Operating Temperature Range . . . . . . . . . . . . . . . . -55 Package Types Storage Temperature Range (TSTG -65 Lead Temperature (During Soldering +265 At Distance 1/16 1/32 Inch (1 ...

Page 5

... Specifications CD4051BMS, CD4052BMS, CD4053BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (Notes 1, 2) Propagation Delay TPHL VDD = 5V, VIN = VDD or GND (Note 1) TPLH VEE = VSS = 0V Address to Signal Out Channels On or Off Propagation Delay TPZH VDD = 5V, VIN = VDD or GND (Note 1) TPZL ...

Page 6

... Specifications CD4051BMS, CD4052BMS, CD4053BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Supply Current IDD VDD = 20V, VIN = VDD or GND N Threshold Voltage VNTH VDD = 10V, ISS = - Threshold Voltage VTN VDD = 10V, ISS = -10 A Delta P Threshold Voltage VTP VSS = 0V, IDD = 10 A ...

Page 7

... Specifications CD4051BMS, CD4052BMS, CD4053BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION OPEN GROUND Static Burn- Note 1 Static Burn- Note 1 Dynamic Burn 12 Note 1 Irradiation 3 Note 2 PART NUMBER CD4052BMS Static Burn- ...

Page 8

... CL = 15pF SWITCHING FREQUENCY (f) (kHz) FIGURE 7. TYPICAL DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4052BMS) (Continued) SUPPLY VOLTAGE (VDD - VEE) = 15V 300 250 200 150 100 10V 50 15V 0 5.0 7.5 10.0 -10.0 -7.5 FIGURE 4. TYPICAL CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) ...

Page 9

... CD4051BMS, CD4052BMS, CD4053BMS VDD = +15V VDD = +7.5V 16 7.5V VSS = 0V VEE = 0V 7 VEE = -7.5V 8 VSS = 0V (a) The ADDRESS (digital-control inputs) and INHIBIT logic levels are: “0” = VSS and “1” = VDD. The analog signal (through the TG) may swing from VEE to VDD VDD = + VSS = 0V ...

Page 10

... CD4051BMS, CD4052BMS, CD4053BMS TRUTH TABLE INPUT STATES CD4051BMS INHIBIT CD4052BMS INHIBIT CD4053BMS INHIBIT ...

Page 11

... VEE VSS tPHL AND tPLH CD4051 OUTPUT RL VDD VSS CLOCK FIGURE 13. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT DIFFERENTIAL CD4052 SIGNALS DIFF MULTIPLEXING FIGURE 14. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052BMS VDD OUTPUT RL VDD VSS CLOCK IN VSS VDD 1 16 50pF VEE ...

Page 12

... CD4051BMS, CD4052BMS, CD4053BMS Chip Dimensions and Pad Layouts CD4051BMSH METALLIZATION: Thickness: 11k PASSIVATION: 10.4kÅ - 15.6k BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. ...

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