S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 24
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S1D13705
Manufacturer Part Number
S1D13705
Description
S1d13705 Embedded Memory Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D13705.pdf
(480 pages)
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5.2 Pin Description
Key:
5.2.1 Host Interface
S1D13705
X27A-A-001-09
Pin Names
AB[16:1]
DB[15:0]
I
O
IO
P
C
CS
COx
TSx
CNx
TEST
AB0
=
=
=
=
=
=
=
=
=
=
Type
Input
Output
Bi-Directional (Input/Output)
Power pin
CMOS level input
CMOS level Schmitt input
CMOS output driver, x denotes driver type (see I
Tri-state CMOS output driver, x denotes driver type (see I
page 25)
CMOS low-noise output driver, x denotes driver type (see I
page 25)
CMOS level test input with pull down resistor
IO
I
I
3, 4, 5, 6, 7,
8, 9, 11, 12,
45, 53, 54,
55, 56, 57,
58, 59, 62,
63, 64, 65,
66, 67, 68,
13, 14, 15,
16, 17, 18,
Pin #
70
69
19
C/TS2
Cell
CS
C
RESET#
State
Input
Input
Hi-Z
This pin has multiple functions.
See Table 5-2: “Host Bus Interface Pin Mapping,” on page 22 for
summary.
These pins input the system address bits 16 through 1 (A[16:1]).
These pins have multiple functions.
See Table 5-2: “Host Bus Interface Pin Mapping,” on page 22 for
summary.
• For SH-3/SH-4 mode, this pin inputs system address bit 0
• For MC68K #1, this pin inputs the lower data strobe (LDS#).
• For MC68K #2, this pin inputs system address bit 0 (A0).
• For Generic #1, this pin inputs system address bit 0 (A0).
• For Generic #2, this pin inputs system address bit 0 (A0).
• For SH-3/SH-4 mode, these pins are connected to [D15:0].
• For MC68K #1, these pins are connected to D[15:0].
• For MC68K #2, these pins are connected to D[31:16] for a
• For Generic #1, these pins are connected to D[15:0].
• For Generic #2, these pins are connected to D[15:0].
(A0).
32-bit device (e.g. MC68030) or D[15:0] for a 16-bit device
(e.g. MC68340).
OL
/I
OH
in Table 6-4: “Output Specifications,” on page 25)
OL
OL
/I
/I
OH
OH
in Table 6-4: “Output Specifications,” on
in Table 6-4: “Output Specifications,” on
Description
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 01/05/22
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