ADP3806 Analog Devices, Inc., ADP3806 Datasheet - Page 13

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ADP3806

Manufacturer Part Number
ADP3806
Description
High-frequency Switch Mode Li-ion Battery Charger
Manufacturer
Analog Devices, Inc.
Datasheet

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drive an external load. The common-mode range of the input
pins is from 4 V to V
ADP3806 that remains active during shutdown. The power to
this block is derived from the bias current on the SYS+ and
SYS− pins.
A separate comparator at the LIMIT pin signals when the
voltage on the ISYS pin exceeds 2.5 V typically. The internal
comparator has an open-drain output that produces the
function shown in the Figure 12 graph of V
LIMIT pin should be externally pulled up to 5 V, 2.5 V, or some
other voltage as needed through a resistor. This graph was taken
with a 50 kΩ pull-up resistor to 5 V and to 2.5 V. When ISYS is
below 2.4 V, the LIMIT pin has high output impedance. The
open-drain output is capable of sinking 700 μA when the
threshold is exceeded. This comparator is turned off during
shutdown to conserve power.
SHUTDOWN
A high impedance CMOS logic input is provided to turn off the
ADP3806. When the voltage on SD is less than 0.8 V, the ADP3806
is placed in low power shutdown. With the exception of the
system current sense amplifier, AMP2, all other circuitry is
turned off. The reference and regulators are pulled to ground
during shutdown and all switching is stopped. During this state,
the supply current is less than 5 A. In addition, the BAT, CS+,
CS−, and SW pins go to high impedance to minimize current
drain from the battery.
UVLO
Undervoltage lock-out, UVLO, is included in the ADP3806 to
ensure proper startup. As V
regulators track V
However, the rest of the circuitry is held off by the UVLO
comparator. The UVLO comparator monitors both regulators
to ensure they are above 5 V before turning on the main charger
circuitry. This occurs when V
regulator outputs ensures that the charger circuitry and driver
stage have sufficient voltage to operate normally. The UVLO
comparator includes 300 mV of hysteresis to prevent
oscillations near the threshold.
CC
until they reach their final voltages.
CC
. This amplifier is the only part of the
CC
CC
rises above 1 V, the reference and
reaches 6 V. Monitoring the
LIMIT
vs. V
ISYS
. The
Rev. C | Page 13 of 16
START-UP SEQUENCE
During a startup from either SD going high or V
the UVLO threshold, the ADP3806 initiates a soft start
sequence. The soft start timing is set by the compensation
capacitor at the COMP pin and an internal 40 μA source.
Initially, both DRVH and DRVL are held low until COMP
reaches 1 V. This delay time is set by
where c
COMP capacitor, t
cycle is very low and then ramps up to its final value with the
same ramp rate given for t
the battery is 10 V when charging is started, the duty cycle is
approximately 65%, corresponding to a VCOMP of ~2 V. The
time for the duty cycle to ramp from 0% at V
at V
current is equal to zero at first, DRVL does not turn on.
However, if the BST capacitor is discharged, DRVL is forced on
for a minimum on time of 200 ns each clock period until the
BST capacitor is charged to greater than 4 V. Typically the BST
capacitor is charged in five to ten clock cycles.
LOOP FEED FORWARD
As described above, the response time at COMP is slowed by
the large compensation capacitor. To speed up the response, two
comparators can quickly feed forward around the normal
control loop and pull the COMP node down to limit any
overshoot in either short-circuit or overvoltage conditions. The
overvoltage comparator has a trip point set to 20% higher than
the final battery voltage. The overcurrent comparator threshold
is set to 180 mV across the CS pins, which is 15% above the
maximum programmable threshold. When these comparators
are tripped, a normal soft start sequence is initiated. The
overvoltage comparator is valuable when the battery is removed
during charging. In this case, the current in the inductor causes
the output voltage to spike up, and the comparator limits the
maximum voltage. Neither of these comparators affects the loop
under normal charging conditions.
COMP
t
DELAY
comp
= 2 V is approximately 5 ms. Because the charge
is the capacitor on the COMP pin. For a 0.22 μF
=
c
comp
40
DELAY
×
μ
A
1
is 5 ms. After this initial delay, the duty
V
DELAY
. For example, if V
COMP
CC
IN
= 1 V to 65%
ADP3806
exceeding
is 16 V and
(4)