CDK1308 Cadeka Microcircuits LLC., CDK1308 Datasheet - Page 14

no-image

CDK1308

Manufacturer Part Number
CDK1308
Description
Ultra Low Power, 20/40/65/80msps, 10-bit Analog-to-digital Converters Adcs
Manufacturer
Cadeka Microcircuits LLC.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CDK1308DILP40
Quantity:
64 320
Data Sheet
Reference Voltages
The reference voltages are internally generated and buff-
ered based on a bandgap voltage reference. No external
decoupling is necessary, and the reference voltages are
not available externally. This simplifies usage of the ADC
since two extremely sensitive pins, otherwise needed, are
removed from the interface.
Operational Modes
The operational modes are controlled with the PD_N and
SLP_N pins. If PD_N is set low, all other control pins are
overridden and the chip is set in Power Down mode. In
this mode all circuitry is completely turned off and the in-
ternal clock is disabled. Hence, only leakage current con-
Mechanical Dimensions
QFN-40 Package
For additional information regarding our products, please visit CADEKA at:
CADEKA Headquarters Loveland, Colorado
T: 970.663.5452
T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
Copyright ©2009 by CADEKA Microcircuits LLC. All rights reserved.
Pin 1 ID - Dia. 0.5
D
(Top Side)
D2
1.14
e
0.45
Pin 0 Exposed Pad
Pin 1 ID - Dia. R
D2
D
b
F
G
L
D1
A2
cadeka.com
1
tributes to the Power Down Dissipation. The startup time
from this mode is longer than for Sleep Mode as all refer-
ences need to settle to their final values before normal
operation can resume.
The SLP_N signal can be used to set the full chip in Sleep
Mode. In this mode internal clocking is disabled, but some
low bandwidth circuitry is kept on to allow for a short
startup time. However, Sleep Mode represents a signifi-
cant reduction in supply current, and it can be used to
save power even for short idle periods.
The input clock should be kept running in all idle modes.
However, even lower power dissipation is possible in Power
Down mode if the input clock is stopped. In this case it is
important to start the input clock prior to enabling active mode.
A
A3
A1
NOTE:
Package dimensions in millimeter unless otherwise noted.
Symbol
D
D
A
A
A
A
D
G
R
b
L
e
F
1
2
3
1
1
2
0.0096
0.001
0.008
0.156
0.012
0.008
0.004
Min
0.008 REF
0.236 BSC
0.226 BSC
0.020 BSC
Inches
0.0004
0.0168
0.023
0.010
0.162
0.016
0.008
A m p l i fy t h e H u m a n E x p e r i e n c e
Typ
0.035
0.002
0.028
0.013
0.167
0.020
0.024
Max
12°
0.00
3.95
0.24
Min
0.2
0.3
0.2
0.1
Millimeters
6.00 BSC
5.75 BSC
0.50 BSC
0.2 REF
0.01
0.65
0.25
4.10
0.42
Typ
0.4
0.2
Max
0.32
0.05
4.25
12°
0.9
0.7
0.5
0.6

Related parts for CDK1308