WM8734 ETC-unknow, WM8734 Datasheet - Page 29

• Manufacturer Part Number: WM8734
• Description: Stereo Audio Codec
• Manufacturer: ETC-unknow

WM8734
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3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
The WM8734 can be controlled using a 3-wire serial interface. SDIN is used for the program data,
SCLK is used to clock in the program data and CSB is use to latch in the program data. The 3-wire
interface protocol is shown in Figure 22.
Figure 22 3-Wire Serial Interface
Notes:
2-WIRE SERIAL CONTROL MODE
The WM8734 supports a 2-wire MPU serial interface. The device operates as a slave device only.
The WM8734 has one of two slave addresses that are selected by setting the state of pin 10, (CSB).
Figure 23 2-Wire Serial Interface
Notes:
Table 17 2-Wire MPU Interface Address Selection
To control the WM8734 on the 2-wire bus the master control device must initiate a data transfer by
establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high.
This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond
to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB
first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of
two available addresses for this device (see table 24). If the correct address is received and the R/W
bit is ‘0’, indicating a write, then the WM8734 will respond by pulling SDIN low on the next clock pulse
(ACK). The WM8734 is a write only device and will only respond to the R/W bit indicating a write. If
the address is not recognised the device will return to the idle condition and wait for a new start
condition and valid address.
Once the WM8734 has acknowledged a correct address, the controller will send eight data bits (bits
B[15]-B[8]). WM8734 will then acknowledge the sent data by pulling SDIN low for one clock pulse.
The controller will then send the remaining eight data bits (bits B[7]-B[0]) and the WM8734 will then
acknowledge again by pulling SDIN low.
1.
2.
1.
2.
CSB STATE
(Default = LOW)
SCLK
SDIN
B[15:9] are Control Address Bits
B[8:0] are Control Data Bits
B[15:9] are Control Address Bits
B[8:0] are Control Data Bits
SCLK
SDIN
CSB
START
0
1
B15
R ADDR
B14
B13
B12
R/W
B11
Address
ACK
B10
0011010
0011011
B9
DATA B15-8
B8
B7
B6
ACK
B5
B4
DATA B7-0
B3
AI Rev 2.2 November 2001
Advanced Information
B2
B1
ACK
B0
STOP
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