AMIS30512 ON Semiconductor, AMIS30512 Datasheet - Page 19

• Manufacturer Part Number: AMIS30512
• Description: Micro-stepping Motor Driver
• Manufacturer: ON Semiconductor

not properly connected to guarantee sufficient low Rdson of
the drivers, then the bit <CPFAIL> is set in Table 27: SPI
Status Register 0. Also after power−on−reset the charge
pump voltage will need the time t
threshold. During that time <CPFAIL> will be set to “1”.
Error Output
microcontroller. The signal on this output is active low and
the logic combination of:
<OVCYij> OR <OPENi> OR <CPFAIL>
Logic Supply Regulator
external decoupling capacitor to supply the digital part of the
Watchdog Function
<WDEN> bit (Table 12: SPI Control Register WR). Once
this bit has been set to “1” (watchdog enable), the
microcontroller needs to re-write this bit to clear an internal
timer before the watchdog timeout interval expires. In case
the timer is activated and WDEN is acknowledged too early
(before t
This is a digital output to flag a problem to the external
NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR
AMIS-30512 has an on-chip 5 V low-drop regulator with
The watchdog function is enabled/disabled through
WDPR
) or not within the interval (after t
V
V
DDH
DDL
VBB
VDD
POR/WD pin
CPU
to exceed the required
Figure 14. Power−on−Reset Timing Diagram
t
PU
WDTO
http://onsemi.com
), then
t
POR
19
chip, some low-voltage analog blocks and external circuitry.
The voltage is derived from an internal bandgap reference.
To calculate the available drive-current for external
circuitry, the specified I
consumption of internal circuitry (unloaded outputs) and the
loads connected to logic outputs. See DC parameters.
Power-On Reset (POR) Function
low” reset for external purposes. At power-up of
AMIS-30512, this pin will be kept low for some time to reset
for example an external microcontroller. A small analog
filter avoids resetting due to spikes or noise on the VDD
supply.
a reset of the microcontroller will occur through POR/WD
pin. In addition, a warm/cold boot bit <WD> is available in
SPI Status Register 0 for further processing when the
external microcontroller is alive again. The watchdog reset
delay t
added to an external delay formed by the pull up resistance
and the capacitive load on the POR/WD pin.
< t
The open drain output pin POR/WD provides an “active
RF
WDRD
t
PD
is determined by an internal delay of 0,5 ms
t
RF
load
should be reduced with the
t
t