AMIS-30521 AMI Semiconductor, Inc., AMIS-30521 Datasheet - Page 16

• Manufacturer Part Number: AMIS-30521
• Description: Micro-stepping Motor Driver
• Manufacturer: AMI Semiconductor, Inc.

AMIS-30521 Micro-stepping Motor Driver
9.0 SPI interface
The serial peripheral interface (SPI) is used to allow external microcontroller (MCU) to communicate with the device. The implemented
SPI block is flexible enough to interface directly with numerous microcontrollers from several manufacturers. AMIS-30521 acts always
as a slave and it can’t initiate any transmission. The operation of the device is configured and controlled by means of SPI registers,
which are observable for read and/or write from the master.
9.1 SPI Transfer Format and Pin Signals
During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (CLK)
synchronizes shifting and sampling of the information on the two serial data lines (DO and DI). DO signal is the output from the slave,
and DI signal is the output from the master. A slave select line (CSB) allows individual selection of a slave SPI device in a multiple-
slave system. The CSB line is active low. If AMIS-30521 is not selected, DO is in high impedance state and it does not interfere with
SPI bus activities. Since AMIS-30521 always clocks data out on the falling edge and samples data in on rising edge of clock, the MCU
SPI port must be configured to match this operation. SPI clock idles low between the transferred bytes.
The diagram below is both a master and a slave timing diagram since CLK, DO and DI pins are directly connected between the master
and the slave.
9.2 Transfer Packet
Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more 8-bit characters (bytes).
The first byte contains command and SPI Register address and will be sent upfront of the packet to indicate to AMIS-30521 the chosen
register and the type of operation.
There are two possible commands for the master in normal operation mode of AMIS-30521:
AMI Semiconductor – June 2007, M-20683-001
www.amis.com
•
•
READ from SPI register:
WRITE to SPI register:
Cmd2
MSB
CLK (Idles Low)
DI (From Master)
DO (From Slave)
Cmd1
data-out shift buffer of AMIS-30521 is updated with new content only at the last (every
Note (1): MSB of data stored on the new address (see Transfer packet). The internal
CSB
Cmd0
Cmd2 = 0
Cmd2 = 1
Command and Address
MSB
Addr4
Figure 14: Timing Diagram of an SPI Transfer
MSB
eighth) falling edge of the CLK signal.
8
7
Addr3
6
6
16
6
5
5
Addr2
5
4
4
4
3
3
Addr1
3
2
2
Addr0
2
1
1
LSB
LSB
LSB
1
MSB
Data7 - Data0
Data byte
(1)
LSB
Data Sheet