AD2S1210 Analog Devices, Inc., AD2S1210 Datasheet
AD2S1210
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AD2S1210 Summary of contents
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... Electric vehicles Integrated starter generators/alternators Automotive motion sensing and control GENERAL DESCRIPTION The AD2S1210 is a complete 10-bit to 16-bit resolution tracking resolver-to-digital converter, integrating an on-board program- mable sinusoidal oscillator that provides sine wave excitation for resolvers. The converter accepts 3.15 V p-p ± 27% input signals, in the range of 2 kHz to 20 kHz on the sine and cosine inputs ...
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... Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 11 Resolver Format Signals ................................................................. 15 Theory of Operation ...................................................................... 16 Resolver to Digital Conversion ................................................. 16 Fault Detection Circuit .............................................................. 16 On-Board Programmable Sinusoidal Oscillator .................... 18 Synthetic Reference Generation ............................................... 18 Configuration of AD2S1210 ......................................................... 20 Modes of Operation ................................................................... 20 Register Map .................................................................................... 21 Position Register ......................................................................... 21 Velocity Register ......................................................................... 21 REVISION HISTORY 8/08—Revision 0: Initial Version ...
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... A, C grades, zero acceleration LSB B, D grades, zero acceleration LSB A, C grades, zero acceleration LSB B, D grades, zero acceleration LSB A, C grades, zero acceleration Bits Hz Hz CLKIN = 8.192 MHz Hz Hz CLKIN = 8.192 MHz Hz Hz CLKIN = 8.192 MHz Hz Hz CLKIN = 8.192 MHz AD2S1210 ...
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... AD2S1210 Parameter Tracking Rate 10-bit 12-bit 14-bit 16-bit Acceleration Error 10-bit 12-bit 14-bit 16-bit Settling Time 10° Step Input 10-bit 12-bit 14-bit 16-bit Settling Time 179° Step Input 10-bit 12-bit 14-bit 16-bit EXC, EXC OUTPUTS Voltage Center Voltage Frequency EXC/EXC DC Mismatch ...
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... The clock frequency of the AD2S1210 can be supplied with a crystal, an oscillator, or directly from a DSP/microprocessor digital output. When using a single-ended clock signal directly from the DSP/microprocessor, the XTALOUT pin should remain open circuit and the logic levels outlined under the logic inputs parameter in Table 1 apply. ...
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... AD2S1210 TIMING SPECIFICATIONS 5.0 V ± 5 MIN Table 2. Parameter Description f Frequency of clock input CLKIN t Clock period ( = 1 and A1 setup time before RD/CS low 1 t Delay CS falling edge to WR/FSYNC rising edge 2 t Address/data setup time during a write cycle 3 t Address/data hold time during a write cycle ...
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... A0 and A1 should remain constant for the duration of the serial readback. This may require 24 clock periods to read back the 8-bit fault information in addition to the 16 bits of position/velocity data. If the fault information is not required, A0/A1 may be released following 16 clock cycles. Limit × × × Rev Page AD2S1210 , T Unit MIN MAX ns min + min CK ns min ns min + min ...
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... AD2S1210 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter AV to AGND, DGND AGND, DGND AGND, DGND DRIVE AGND to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Analog Output Voltage Swing 1 Input Current to Any Pin Except Supplies ...
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... AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis Digital Supply Voltage, 4. 5.25 V. This is the supply voltage for all digital circuitry on the AD2S1210. The AV DD voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. ...
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... SINLO Negative Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4 Analog Supply Voltage, 4. 5.25 V. This pin is the supply voltage for all analog circuitry on the AD2S1210. The DD AV and DV voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a ...
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... Figure 7. Typical 12-Bit Angular Accuracy Histogram of Codes, 512 Samples, 2048 2049 Figure 8. Typical 10-Bit Angular Accuracy Histogram of Codes, 512 Samples, Rev Page CODE Hysteresis Disabled 0 510 511 512 513 CODES Hysteresis Enabled CODE Hysteresis Disabled AD2S1210 514 ...
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... AD2S1210 600 500 400 300 200 100 0 126 127 128 CODES Figure 9. Typical 10-Bit Angular Accuracy Histogram of Codes, 512 Samples, Hysteresis Enabled TIME (ms) Figure 10. Typical 16-Bit 10° Step Response ...
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... Rev Page AD2S1210 10-BIT 14-BIT 12-BIT 16-BIT 10 100 1k 10k FREQUENCY (Hz) Figure 18. Typical System Magnitude Response 10-BIT 14-BIT 12-BIT 16-BIT 10 100 1k 10k FREQUENCY (Hz) Figure 19. Typical System Phase Response 500 1000 ...
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... AD2S1210 5000 10000 15000 20000 25000 30000 35000 40000 45000 2 ACCELERATION (rps ) Figure 21. Typical 14-Bit Tracking Error vs. Acceleration 20000 60000 100000 2 ACCELERATION (rps ) Figure 22. Typical 12-Bit Tracking Error vs. Acceleration ...
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... Resolver format signals refer to the signals derived from the output of a resolver, as shown in Equation 1. Figure 25 illustrates the output format. (1) S2 – S4 (cos) S3 – S1 (sin) R2 – R4 (REF) Rev Page AD2S1210 × sin(ω × sin(ωt) × cos(θ ...
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... LOS sine/cosine threshold, the electrical angle through which the resolver may rotate before the LOS can be detected by the AD2S1210 is referred to as the LOS angular latency. This is defined by the specified LOS sine/ cosine threshold set by the user and the maximum amplitude of the input signals being applied to the AD2S1210 ...
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... CLKIN/2. The AD2S1210 detects an LOS or DOS due to the resolver inputs (sine or cosine) falling below or exceeding the LOS and DOS thresholds within two window counter periods. For example, with an excitation frequency of 10 kHz, a fault is detected within 125 μ ...
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... Sine/Cosine Input Clipping The AD2S1210 indicates that a clipping error has occurred if any of the resolver input pins (SIN, SINLO, COS, or COSLO) are clipping the power rail or ground rail of the AD2S1210. The clipping fault is indicated if the input amplitudes are less than 0. greater then AV − ...
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... V DRIVE 10nF Figure 26. Connecting the AD2S1210 to a Resolver In this recommended configuration, the converter introduces offset in the SIN, SINLO, COS, and COSLO signal outputs REF from the resolver. The sine and cosine signals can each be connected to a different potential relative to ground if the sine and cosine signals adhere to the recommended specifications ...
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... AD2S1210 is in configuration mode and to determine whether the position or velocity data is supplied to the output pins, see Table 8. Setting the Excitation Frequency The excitation frequency of the AD2S1210 is set by writing a frequency control word to the excitation frequency register, Address 0x91 (see the Register Map section). ( × ...
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... Read only The LOS threshold register determines the loss of signal threshold of the AD2S1210. The AD2S1210 allows the user to set the LOS threshold to a value between 0 V and 4.82 V. The resolution of the LOS threshold is seven bits, that is, 38 mV. Note that the MSB, D7, should be set to 0 ...
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... FCW is the frequency control word and f frequency of the AD2S1210. The specified range of the excitation frequency is from 2 kHz to 20 kHz and can be set in increments of 250 Hz. To ensure that the AD2S1210 is operated within the specified frequency range, the frequency control word should be a value between 0x4 and 0x50. ...
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... The MSB (D7) of each register address defined on the AD2S1210 is high. The MSB of each data word written to the AD2S1210 is low. Note that when a data word is written to the AD2S1210, the MSB is internally reconfigured as a parity bit. When reading ...
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... The MSB (D7) of each register address defined on the AD2S1210 is high (see the Register Map section). The MSB of each data word written to the AD2S1210 is low. To write to one of the registers, the user must first place the AD2S1210 into configura- tion mode using the A0 and A1 inputs. Then the 8-bit address should be written to the AD2S1210 using Pin DB7 to Pin DB0, and latched using the rising edge of the WR / FSYNC input ...
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... Clearing the Fault Register The LOT pin and/or the DOS pin of the AD2S1210 are taken low to indicate that a fault has been detected. The AD2S1210 is capable of detecting eight separate fault conditions. To determine which condition triggered the fault indication, the user is required to enter configuration mode and read the fault register. To reset the fault indicators, an additional SAMPLE pulse is required ...
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... AD2S1210 f CLKIN CLKIN A0 DB0 TO DB7 NOTES 1. DON’T CARE. f CLKIN CLKIN t 16 SAMPLE CS RD A0, A1 DATA *ASSUMES FAULT REGISTER ADDRESS WRITTEN TO PART BEFORE EXITING CONFIGURATION MODE. NOTES 1. DON’T CARE 14B 14A ...
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... CLKIN CLKIN t 16 SAMPLE A0, A1 DATA NOTES 1. DON’T CARE. Figure 31. Parallel Port—Clear Fault Register CONFIGURATION 14A t 19 FAULT ADDRESS FAULT DATA Rev Page AD2S1210 ...
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... If the user does not require the fault information, the WR / FSYNC can be pulled high after the16 Clearing the Fault Register The LOT pin and/or the DOS pin of the AD2S1210 are taken low to indicate that a fault has been detected. The AD2S1210 is capable of detecting eight separate fault conditions. To determine which condition triggered the fault indication, the user is required to enter configuration mode and read the fault register ...
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... Figure 34. Serial Interface Read Timing—Configuration Mode f SCLK DATA OLD DATA ADDRESS 2 DATA 1 Rev Page AD2S1210 t 29 LSB LSB NEW ADDRESS COPY OF DATA ADDRESS 3 DATA 2 ...
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... AD2S1210 f CLKIN CLKIN t 16 SAMPLE CS WR/FSYNC A0, A1 SDO *ASSUMES FAULT REGISTER ADDRESS WRITTEN TO PART BEFORE EXITING CONFIGURATION MODE. NOTES 1. DON’T CARE POSITION VELOCITY t 23 POSITION VELOCITY Figure 35. Serial Interface Read Timing Rev Page ...
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... Figure 36 and NM Timing for Clockwise Rotation The inclusion of A and B outputs allows the AD2S1210 with resolver solution to replace optical encoders directly without the need to change or upgrade existing application software. SUPPLY SEQUENCING AND RESET The AD2S1210 requires an external reset signal to hold the ...
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... MHz ≈ 244 ns). Substitution yields the open-loop transfer function, G(s). G This transformation produces the best matching at low frequencies (f < f SAMPLE bandwidth of the AD2S1210), the transfer function can be simplified to G (10) where (11) ...
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... Tracking The units of the numerator and denominator must be consistent. The maximum acceleration of the AD2S1210 is defined by the maximum acceptable tracking error in the users application. For example, if the maximum acceptable tracking error is 5°, then the maximum acceleration is defined as the acceleration that creates an output position error of 5° ...
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... PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 AD2S1210ASTZ −40°C to +85°C 1 AD2S1210BSTZ −40°C to +85°C AD2S1210CSTZ 1 −40°C to +125°C 1 AD2S1210DSTZ −40°C to +125° RoHS Compliant Part. 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0. PIN 1 TOP VIEW 0.20 (PINS DOWN) 0.09 7° ...
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... NOTES Rev Page AD2S1210 ...
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... AD2S1210 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07467-0-8/08(0) Rev Page ...