ad1890jpz Analog Devices, Inc., ad1890jpz Datasheet
ad1890jpz
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ad1890jpz Summary of contents
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... There is no need to explicitly select or program the input and output sample clock frequencies, as the AD1890/AD1891 automatically sense the relationship between SamplePort and SamplePorts are trademarks of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable ...
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AD1890/AD1891–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltage +5.0 Ambient Temperature 25 MCLK 20 Load Capacitance 100 All minimums and maximums tested except as noted. PERFORMANCE (Guaranteed over 0 C AD1890 Dynamic Range ( kHz, –60 dB ...
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POWER ( MCLK = 16 MHz Supplies Voltage Current 5 Current 3 Dissipation Operation ( Operation ...
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AD1890/AD1891 (continued from Page 1) PRODUCT OVERVIEW (Continued) automatically limited to avoid alias distortion on the output sig- nal. The AD1890/AD1891 dynamically alter the low-pass filter cutoff frequency smoothly and slowly, so that real-time varia- tions in the sample rate ...
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DEFINITIONS Dynamic Range The ratio of a near full-scale input signal to the integrated noise in the passband ( kHz), expressed in decibels (dB). Dy- namic range is measured with a –60 dB input signal and “60 dB” ...
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AD1890/AD1891 Output Control Signals Pin Name Number I/O Description BKPOL_O 19 I Bit clock polarity. LO: Normal mode. Output data is valid on rising edges of BCLK_O, changed on falling. HI: Inverted mode. Output data is valid on falling edges ...
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THEORY OF OPERATION There are at least two logically equivalent methods of explaining the concept of asynchronous sample rate conversion: the high speed interpolation/decimation model and the polyphase filter bank model. Using the AD1890 and AD1891 SamplePorts does not require ...
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AD1890/AD1891 Polyphase Filter Bank Model Although less intuitively understandable than the interpolation/ decimation model, the polyphase filter bank model is useful to explore because it more accurately portrays the operation of the actual AD1890/AD1891 SamplePort hardware. In the polyphase filter ...
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AMP Figure 3. Four Polyphase Subfilters Realigned to Coarse Time Grid PARALLEL POLYPHASE FILTER BANK POLYPHASE FILTER 1 POLYPHASE FILTER 2 POLYPHASE FILTER 3 POLYPHASE FILTER 4 POLYPHASE FILTER 5 POLYPHASE FILTER 6 INPUT POLYPHASE FILTER 7 SIGNAL POLYPHASE FILTER ...
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AD1890/AD1891 Asynchronous sample rate conversion under the polyphase filter bank model is accomplished by selecting the output of a particu- lar polyphase filter on the basis of the temporal relationship be- tween the input sample clock and the output sample ...
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Sample Clock Jitter Rejection The loop filter settling time also affects the ability of the AD1890/AD1891 ASRCs to reject sample clock jitter, since the control loop effectively computes a time weighted average or “estimated” new output of many past input ...
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AD1890/AD1891 Cutoff Frequency Modification The final important operating concept of the ASRCs is the mod- ification of the filter cutoff frequency when the output sample rate (F ) drops below the input sample rate (F SOUT during downsampling operation. The ...
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OPERATING FEATURES Serial Input/Output Ports The AD1890/AD1891 use the frequency of the left/right input clock (LR_I) and the left/right output clock (LR_O) signals to determine the sample rate ratio, and therefore these signals must run continuously and transition twice per ...
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AD1890/AD1891 APPLICATION ISSUES Dither Due to the large output word length, no redithering of the AD1890/AD1891 output is necessary. This assumes that the input is properly dithered and the user retains the same or greater number of output bits as ...
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Multiple ASRC Synchronization and Performance Degradation Multiple parallel AD1890/AD1891 ASRCs may be used in a single system. Multiple AD1890/AD1891s can be “synchro- nized” by simply sharing the same reset and MCLK lines, and ensuring that all the ASRCs leave the ...
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AD1890/AD1891 Performance Graphs –60.00 –70.00 –80.00 –90.00 –100.0 –110.0 –120.0 –130.0 –140.0 –150.0 –160.0 20 100 FREQUENCY – Hz Figure 14a. AD1890—Dynamic Range from kHz, –60 dBFS, 48 kHz Input Sample Frequency, 44.1 kHz Output Sample ...
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FREQUENCY – Hz Figure 17a. AD1890—THD+N vs. Frequency, 48 kHz Input Sample Frequency, 44.1 kHz Output Sample Frequency, Full-Scale Input Signal –90.00 –95.00 –100.0 –105.0 –110.0 –115.0 –120.0 –125.0 ...
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AD1890/AD1891 0.0 –20.00 –40.00 –60.00 –80.00 –100.0 –120.0 –140 10k 12k FREQUENCY – Hz Figure 20a. AD1890—Twintone, 10 kHz and 11 kHz, 44.1 kHz Input Sample Frequency, 48 kHz Output Sample Frequency, 16k-Point FFT, BH4 ...
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BCLK_I, BCLK_O NORMAL MODE INPUT BCLK_I, BCLK_O INVERTED MODE LR_I, LR_O INPUT DATA IN/OUT MSB MSB-1 NO MSB DELAY MODE DATA IN/OUT MSB MSB–1 MSB–2 MSB DELAY MODE Figure 23. AD1890/AD1891 Serial Data Input and Output Timing, Left/ Right Clock ...
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AD1890/AD1891 28 PIN 1 1 0.250 (6.35) MAX 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.048 (1.21) 0.042 (1.07) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). N-28 28-Lead Plastic DIP 15 0.580 (14.73) 0.485 (12.32) 14 1.565 (39.70) ...