ad1890jpz Analog Devices, Inc., ad1890jpz Datasheet - Page 13

• Manufacturer Part Number: ad1890jpz
• Description: Sampleport Stereo Asynchronous Sample Rate Converters
• Manufacturer: Analog Devices, Inc.

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OPERATING FEATURES
Serial Input/Output Ports
The AD1890/AD1891 use the frequency of the left/right input
clock (LR_I) and the left/right output clock (LR_O) signals to
determine the sample rate ratio, and therefore these signals must
run continuously and transition twice per sample period. (The
LR_I clock frequency is equivalent to F
frequency is equivalent to F
WCLK_O, BCLK_I, BCLK_O) are edge sensitive and may be
used in a gated or burst mode (i.e., a stream of pulses during
data transmission or reception followed by periods of inactivity).
The word clocks and bit clocks are used only to write data into
or read data out of the serial ports; only the left/right clocks are
used in the internal DSP blocks. It is important that the left/
right clocks are “clean” with monotonic rising and falling edge
transitions and no excessive overshoot or undershoot which
could cause false triggering on the AD1890/AD1891.
The AD1890/AD1891’s flexible serial input and output ports
consume and produce data in twos-complement, MSB-first
format. The left channel data field always precedes the right
channel data field; the current channel being consumed or pro-
duced is indicated by the state of the left/right clock (LR_I and
LR_O). A left channel field, right channel field pair is called a
frame. The input data field consists of 4 to 20 bits for the
AD1890, and 4 to 16 bits for the AD1891. The output data
field consists of 4 to 24 bits for both devices. The input signals
are specified to TTL logic levels, and the outputs swing to full
CMOS logic levels. The ports are configured by pin selections.
Serial I/O Port Modes
The AD1890/AD1891 has pin-selectable bit clock polarity for
the input and output ports. In “normal” mode (BKPOL_I or
BKPOL_O LO) the data is valid on the rising edge. In the
“inverted” mode (BKPOL_I or BKPOL_O HI) the data is
valid on the falling edge. Both modes are shown in Figures 22
and 23.
In the pin selectable MSB delay mode, which can be set inde-
pendently for the input and output ports, the MSB is delayed by
one bit clock. This is useful for I
ease of interfacing to some DSP processors. Both the MSB de-
lay mode (MSBDLY_I or MSBDLY_O HI) and the MSB
non-delay mode (MSBDLY_I or MSBDLY_O LO) are shown
in Figures 22 and 23.
The AD1890/AD1891 SamplePort serial ports operate in either
the word clock (WCLK_I, WCLK_O) triggered mode or left/
right clock (LR_I, LR_O) triggered mode. These modes can be
utilized independently for the input and output ports, by reset-
ting or setting the TRGLR_I and TRGLR_O control lines
respectively. In the word clock triggered mode, as shown in Fig-
ure 22, after the left/right clock is valid, the appearance of the
MSB of data is synchronous with the rising edge of the word
clock (or delayed by one bit clock if the MSB delay mode is
selected). Note that the word clock is rising edge sensitive, and
can fall anytime after it is sampled HI by the bit clock. In the
left/right clock triggered mode, as shown in Figure 23, the
SOUT
.) The other clocks (WCLK_I,
2
S format compatibility and for
SIN
and the LR_O clock
–13–
appearance of the MSB of data is synchronous with the rising
edge of the left/right clock for the left channel and the falling
edge of left/right clock for the right channel. The MSB is
delayed by one bit clock after the left/right clock if the MSB
delay mode is selected. The word clock is not required in the
left/right clock triggered mode, and should be tied either HI or
LO. Figure 23 shows the bit clock in the optional gated or burst
mode; the bit clock is inactive between data fields, and can take
either the HI state or the LO state while inactive.
Note that there is no requirement for a delay between the left
channel data and the right channel data. The left/right clocks
and the word clocks can transition immediately after the LSB of
the data, so that the MSB of the subsequent channel appears
without any timing delay. The AD1891 is therefore capable of a
32-bit frame mode, in which both 16-bit channels are packed
into a 32-bit clock period. More generally, there is no particular
requirement for when the left/right clock falls (i.e., there is no
left/right clock duty cycle or pulse width specification), provided
that the left/right clock frequency equals the intended sample
frequency, and there are sufficient bit clock periods to clock in
or out the intended number of data bits.
Control Signals
The GPDLYS, SETLSLW, BKPOL_I, BKPOL_O, TRGLR_I,
TRGLR_O, MSBDLY_I, and MSBDLY_O inputs are asyn-
chronous signals in that they need obey no particular timing
relation to MCLK or the sample clocks. Ordinarily, these pins
are hardwired or connected to an I/O register for microprocessor
control. The only timing requirement on these pins is that the
control signals are stable and valid before the first serial input
data bit (i.e., the MSB) is presented to the AD1890/AD1891.
Reset
Figure 25 shows the reset timing for the AD1890/AD1891
SamplePorts. MCLK must be running when RESET is
asserted, and the bit clocks, the word clocks and the left/right
clocks may also be running. When the AD1890/AD1891 come
out of reset, they default to a F
ter pipeline is not cleared. However, the mute output goes HI
for at least 128 cycles, adequate to allow the pipeline to clear. If
F
sample clock servo control loop also has to settle. While settling,
the mute output will be HI. After the external system resets the
AD1890/AD1891, it should wait until the mute output goes LO
before clocking in serial data.
There is no requirement for using the RESET pin at power-up
or when the input or output sample rate changes. If it is not
used, the AD1890/AD1891 will settle to the sample clocks sup-
plied within 200 ms in fast-settling mode or within 800 ms in
slow-settling mode.
SIN
differs significantly from F
SIN
SOUT
AD1890/AD1891
to F
, then the AD1890/AD1891
SOUT
ratio of 1:1. The fil-