ad1890jpz Analog Devices, Inc., ad1890jpz Datasheet - Page 5

• Manufacturer Part Number: ad1890jpz
• Description: Sampleport Stereo Asynchronous Sample Rate Converters
• Manufacturer: Analog Devices, Inc.

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DEFINITIONS
Dynamic Range
The ratio of a near full-scale input signal to the integrated noise
in the passband (0 to 20 kHz), expressed in decibels (dB). Dy-
namic range is measured with a –60 dB input signal and
“60 dB” arithmetically added to the result.
Total Harmonic Distortion + Noise
Total Harmonic Distortion plus Noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the val-
ues of the harmonics and noise to the rms value of a sinusoidal
input signal. It is usually expressed in percent (%) or decibels.
Interchannel Phase Deviation
Difference in input sampling times between stereo channels, ex-
pressed as a phase difference in degrees between 1 kHz inputs.
AD1890/AD1891 PIN LIST
Serial Input Interface
NOTE
1
Pin Name Number
DATA_I
BCLK_I
WCLK_I
LR_I
Serial Output Interface
Pin Name Number
DATA_O
BCLK_O
WCLK_O
LR_O
Input Control Signals
Pin Name Number
BKPOL_I
TRGLR_I
MSBDLY_I 12
The beginning of valid data will be delayed by one BLCK_I if MSBDEL_I is selected (HI).
10
3
4
5
6
23
26
25
24
11
I/O
I
I
I
I
I/O
O
I
I
I
I/O
I
I
I
(TRGLR_I = LO) indicates the beginning of valid input data. Included for I
compatibility. LO: No delay.
Description
Serial input, MSB first, containing two channels of 4- to 20-bits of twos-complement data per
channel. AD1891 ONLY: Maximum of 16 data bits per channel; additional bits ignored.
Bit clock input for input data.
Word clock input for input data. This input is rising edge sensitive. (Not required in LR input data
clock triggered mode [TRGLR_I = HI].)
Left/right clock input for input data. Must run continuously.
Description
Serial output, MSB first, containing two channels of 4- to 24-bits of twos-complement data per
channel.
Bit clock input for output data.
Word clock input for output data. This input is rising edge sensitive. (Not required in LR output
data clock triggered mode [TRGLR_O = HI].)
Left/right clock input for output data. Must run continuously.
Description
Bit clock polarity. LO: Normal mode. Input data is sampled on rising edges of BCLK_I. HI:
Inverted mode. Input data is sampled on falling edges of BCLK_I.
Trigger on LR_I. HI: Changes in LR_I indicate beginning
WCLK_I indicates beginning of valid input data.
MSB delay. HI: Input data is delayed one BCLK_I after either LR_I (TRGLR_I = HI) or WCLK_I
–5–
Group Delay
Intuitively, the time interval required for a full-level input pulse
to appear at the converter’s output, at full level, expressed in
milliseconds (ms). More precisely, the derivative of radian phase
with respect to radian frequency at a given frequency.
Transport Delay
The time interval between when an impulse is applied to the
converters input and when the output starts to be affected by
this impulse, expressed in milliseconds (ms). Transport delay is
independent of frequency.
1
of valid input data. LO: Rising edge of
AD1890/AD1891
2
S data format