ad1890jpz Analog Devices, Inc., ad1890jpz Datasheet - Page 11

• Manufacturer Part Number: ad1890jpz
• Description: Sampleport Stereo Asynchronous Sample Rate Converters
• Manufacturer: Analog Devices, Inc.

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Sample Clock Jitter Rejection
The loop filter settling time also affects the ability of the
AD1890/AD1891 ASRCs to reject sample clock jitter, since the
control loop effectively computes a time weighted average or
“estimated” new output of many past input and output clock
events. This first order low pass filtering of the sample clock
ratio provide the AD1890/AD1891 with their jitter rejection
characteristic. In the slow settling mode, the AD1890/AD1891
attenuate jitter frequencies higher than 3 Hz ( 800 ms for the
control loop to settle to an 18-bit “pure” sine wave), and thus
reject all but the most severe sample clock jitter; performance is
essentially limited only by the FIR filter. In the fast settling
mode, the ASRCs attenuate jitter components above 12 Hz
( 200 ms for the control loop to settle). Due to the effects of
on-chip synchronization of the sample clocks to the 16 MHz
(62.5 ns) MCLK master clock, sample clock jitter must be a
large percentage of the MCLK period (>10 ns) before perfor-
mance degrades in either the slow or fast settling modes. Note
that since both past input and past output clocks are used to
compute the filtered “current” internal output clock request, jit-
ter on both the input sample clock and the output sample clock
is rejected equally. In summary: the fast settling mode is best for
applications when the sample rates will be dynamically altered
(e.g., varispeed situations) while the slow settling mode provides
the most sample clock jitter rejection.
Clock jitter can be modeled as a frequency modulation process.
Figure 7 shows one such model, where a noise source combined
with a sine wave source modulates the “carrier” frequency gen-
erated by a voltage controlled oscillator.
If the jittered output of the VCO is used to clock an analog-to-
digital converter, the digital output of the ADC will be contami-
nated by the presence of jitter. If the noise source is spectrally
flat (i.e., “white” jitter), then an FFT of the ADC digital output
would show a spectrum with a uniform noise floor which is el-
evated compared to the spectrum with the noise source turned
off. If the noise source has distinct frequency components (i.e.,
“correlated” jitter), then an FFT of the ADC digital output
would show symmetrical sidebands around the ADC input sig-
nal, at amplitudes and frequencies determined by frequency
modulation theory. One notable result is that the level of the
noise or the sidebands is proportional to the slope of the input
signal, i.e., the worst case occurs at the highest frequency full-
scale input (a full-scale 20 kHz sinusoid).
The AD1890/AD1891 apply rejection to these jitter frequency
components referenced to the input signal. In other words, if a
VOLTAGE
SOURCE
Figure 7. Clock Jitter Modeled as a Modulated VCO
WAVE
SINE
NOISE SOURCE
ANALOG IN
NOISE
WAVEFORM
VCO
ADC
DIGITAL
OUT
–11–
5 kHz digital sinusoid is applied to the ASRC, depending on the
settling mode selected, the ASRC will attenuate sample clock
jitter at either 3 Hz above and below 5 kHz (slow settling) or
12 Hz above and below 5 kHz (fast settling). The rolloff is 6 dB
per octave. As an example, suppose there was correlated jitter
present on the input sample clock with a 1 kHz component,
associated with the same 5 kHz sinusoidal input data. This
would produce sidebands at 4 kHz and 6 kHz, 3 kHz and
7 kHz, etc., with amplitudes that decrease as they move away
from the input signal frequency. For the slow settling mode
case, 1 kHz represents more than nine octaves (relative to
3 Hz), so the first two sideband pairs would be attenuated by
more than 54 dB. For the fast settling mode case, 1 kHz repre-
sents more than seven octaves (relative to 12 Hz), so that the
first two sideband pairs would be attenuated by more than
42 dB. The second and higher sideband pairs are attenuated
even more because they are spaced further from the input signal
frequency.
Group Delay Modes
The other parameter that determines the likelihood of FIFO in-
put overflow or output underflow is the FIFO depth. This is the
parameter that is selected by the GPDLYS pin (AD1890 only;
this pin is a No Connect for the AD1891). The drawback with
increasing the FIFO depth is increasing the device’s overall
group delay, but most applications are insensitive to a small in-
crease in group delay. [This FIFO-induced group delay is better
termed transport delay, since it is frequency independent, and
should be kept conceptually distinct from the notion of group
delay as used in the polyphase filter bank model. The total
group delay of the AD1890/AD1891 equals the FIFO transport
delay plus the FIR (polyphase) filter group delay.]
In the short group delay mode, the FIFO read and write point-
ers are separated by five memory locations ( 100 s equivalent
transport delay at a 50 kHz sample rate). This is added to the
FIR filter delay (64 taps divided by 2) for a total nominal group
delay in short mode of 700 s. The short group delay mode is
useful when the input and output sample clocks are asynchro-
nous but either do not vary or change very slowly.
In the long group delay mode (AD1890 only, the AD1891 is
always in the short group delay mode), the FIFO read and write
pointers are separated by 96 memory locations ( 2 ms equiva-
lent transport delay). This is added to the FIR filter delay
(64 taps divided by 2) for a total nominal group delay in long
mode of 3 ms. The long group delay mode is useful when the
input and output sample clocks are asynchronous and changing
relative to one another, such as during varispeed effects.
These delays are deterministic and constant except when F
drops below F
increase (see “Cutoff Frequency Modification” below). In either
mode, if the FIFO read and write addresses cross, the MUTE_O
signal will be asserted. Note that in all modes and under all con-
ditions, both the highly oversampled low-pass prototype and the
polyphase subfilters of the AD1890/AD1891 ASRCs possess a
linear phase response.
The AD1890 has been designed so that when it is in long group
delay mode and fast settling mode, a full 2:1 step change (i.e.,
occurring between two samples) in sample frequency ratio can
be tolerated without output mute.
SIN
which causes the number of FIR filter taps to
AD1890/AD1891
SOUT