ad1890jpz Analog Devices, Inc., ad1890jpz Datasheet - Page 14

• Manufacturer Part Number: ad1890jpz
• Description: Sampleport Stereo Asynchronous Sample Rate Converters
• Manufacturer: Analog Devices, Inc.

AD1890/AD1891
APPLICATION ISSUES
Dither
Due to the large output word length, no redithering of the
AD1890/AD1891 output is necessary. This assumes that the
input is properly dithered and the user retains the same or
greater number of output bits as there are input bits. The
AD1890/AD1891 output bit stream may thus be used directly
as the input to downstream digital audio processors, storage
media or output devices.
If the AD1890/AD1891 is to be used to dramatically down-
sample (i.e., output sample frequency is much lower than input
sample frequency), the input should be sufficiently dithered to
account for the limiting of the input signal bandwidth (which
reduces the RMS level of the input dither). No dither is inter-
nally used or applied to the audio data in the AD1890/AD1891
SamplePorts.
Decoupling and PCB Layout
The AD1890/AD1891 ASRCs have two power (Pins 7 and 22)
and two ground (Pins 8 and 21) connections to minimize output
switching noise and ground bounce. [Pins 14 and 27 are actu-
ally control inputs, and should be tied LO, but need not be
decoupled.] The DIP version places these pins at the center of
the device to optimize switching performance. The AD1890/
AD1891 should be decoupled with two high quality 0.1 F or
0.01 F ceramic capacitors (preferably surface mount chip
capacitors, due to their low inductance), one between each V
GND pair. Best practice PCB layout and interconnect guide-
lines should be followed. This may include terminating MCLK
or the bit clocks if excessive overshoot or undershoot is evident
and avoiding parallel PCB traces to minimize digital crosstalk
between clocks and control lines. Note that DIP and PLCC
sockets reduce electrical performance due to the additional in-
ductance they impose; sockets should therefore be used only
when required.
Master Clock
Using a 16 MHz MCLK, the nominal range of sample frequen-
cies that the AD1890/AD1891 accept is from 8 kHz to 56 kHz.
Other sample frequency ranges are possible by linearly scaling
the MCLK frequency. For example, a 12 MHz MCLK would
yield a sample frequency range of 6 kHz to 42 kHz, and a
20 MHz MCLK would yield a sample frequency range of
10 kHz to 70 kHz. The approximate relative upper bound
sample frequency is the MCLK frequency divided by 286; the
approximate relative lower bound sample frequency is the
MCLK frequency divided by 2000. The audio performance will
not degrade if the sample frequencies are kept within these
bounds. The AD1890/AD1891 SamplePorts are production
tested with a 20 MHz MCLK. Note that due to MCLK-driven
finite register length constraints, there is a minimum input
sample frequency (LR_I). The allowable input and output
sample frequency ranges for MCLK frequencies of 20 MHz,
16 MHz and 12 MHz are shown in Figures 9, 10 and 11.
DD
/
–14–
Figure 9. Allowable Input and Output Sample Frequencies
MCLK = 20 MHz Case
Figure 10. Allowable Input and Output Sample Frequencies
MCLK = 16 MHz Case
Figure 11. Allowable Input and Output Sample Frequencies
MCLK = 12 MHz Case
80
72
64
56
48
40
32
24
16
80
72
64
56
48
40
32
24
16
80
72
64
56
48
40
32
24
16
8
0
8
0
8
0
0
0
0
6kHz
8kHz
10kHz
8
8
8
42kHz
56kHz
16
16
16
70kHz
SAMPLING
24
24
24
UP-
SAMPLING
UPSAMPLING
DOWN-
32
32
32
UPSAMPLING
F sin /F sout = 1/2
F sin /F sout = 1/2
F sin – kHz
F sin /F sout = 1/2
F sin – kHz
F sin – kHz
DOWNSAMPLING
40
40
40
42kHz
48
48
DOWNSAMPLING
48
56
56
56
56kHz
70kHz
64
64
64
F sin /F sout = 1/1
F sin /F sout = 1/1
F sin /F sout = 1/1
72
72
72
80
80
80
F sin /F sout = 2/1
F sin /F sout = 2/1
F sin /F sout = 2/1
REV. 0