ad1890jpz Analog Devices, Inc., ad1890jpz Datasheet - Page 4

• Manufacturer Part Number: ad1890jpz
• Description: Sampleport Stereo Asynchronous Sample Rate Converters
• Manufacturer: Analog Devices, Inc.

AD1890/AD1891
(continued from Page 1)
PRODUCT OVERVIEW (Continued)
automatically limited to avoid alias distortion on the output sig-
nal. The AD1890/AD1891 dynamically alter the low-pass filter
cutoff frequency smoothly and slowly, so that real-time varia-
tions in the sample rate ratio are possible without degradation of
the audio quality.
The AD1890/AD1891 have a pin selectable slow- or fast-settling
mode. This mode determines how quickly the ASRCs adapt to a
change in either the input sample clock frequency (F
output sample clock frequency (F
mode, the control loop which computes the ratio between F
and F
jitter above 3 Hz. The slow-settling mode offers the best signal
quality and the greatest jitter rejection. In the fast-settling mode,
the control loop settles in approximately 200 ms and begins to
reject jitter above 12 Hz. The fast-settling mode allows rapid,
real time sample rate changes to be tracked without error, at the
expense of some narrow-band noise modulation products on the
output signal.
The AD1890 also has a pin selectable, short or long group delay
mode. This pin determines the depth of the First-In, First-Out
(FIFO) memory which buffers the input data samples before
they are processed by the FIR convolver. In the short mode, the
group delay is approximately 700 s. The ASRC is more sensi-
tive to sample rate changes in this mode (i.e., the pointers which
manage the FIFO are more likely to cross and become momen-
tarily invalid during a sample rate step change), but the group
delay is minimized. In the long mode, the group delay is ap-
proximately 3 ms. The ASRC is tolerant of large dynamic
sample rate changes in this mode, and it should be used when
the device is required to track fast sample rate changes, such as
in varispeed applications. The AD1891 features the short group
delay mode only. In either device, if the read and write pointers
that manage the FIFO cross (indicating underflow or overflow),
the ASRC asserts the mute output (MUTE_O) pin HI for 128
output clock cycles. If MUTE_O is connected to the mute input
(MUTE_I) pin, as it normally should be, the serial output will
be muted (i.e., all bits zero) during this transient event.
The AD1890/AD1891 are fabricated in a 0.8 m single poly,
double metal CMOS process and are packaged in a 0.6" wide
28-pin plastic DIP and a 28-pin PLCC. The AD1890/AD1891
operate from a +5 V power supply over the temperature range of
0 C to +70 C.
SOUT
settles in approximately 800 ms and begins to reject
SOUT
). In the slow-settling
SIN
) or the
SIN
–4–
GPDLYS (AD1890)
N/C (AD1891)
BKPOL_I
TRGLR_I
WCLK_I
MSBDLY_I
BKPOL_I
TRGLR_I
LR_I
GND
WCLK_I
V
DATA_I
BCLK_I
RESET
N/C
DD
MCLK
GND
GND
LR_I
V
N/C
DD
10
11
5
6
7
8
9
N/C = NO CONNECT
10
11
12
13
14
AD1890/AD1891 PLCC Pinout
1
2
3
4
5
6
7
8
9
12
AD1890/AD1891 DIP Pinout
4
N/C = NO CONNECT
13
SERIAL IN
3
FIFO
FIFO
14
2
TRACKING
ACCUM
SERIAL IN
CLOCK
TRACKING
MULT
CLOCK
15
1
MULT
AD1890/AD1891
COEF ROM
SERIAL OUT
ACCUM
SERIAL OUT
16
28
AD1890/AD1891
COEF ROM
27
17
18
26
25
24
23
22
21
20
19
28
27
26
25
24
23
22
21
20
19
18
17
16
15
WCLK_O
LR_O
DATA_O
V
GND
N/C
BKPOL_O
DD
SETSLW
GND
BCLK_O
WCLK_O
LR_O
DATA_O
V
GND
N/C
BKPOL_O
TRGLR_O
MSBDLY_O
MUTE_O
MUTE_I
REV. 0
DD