KSZ8862 Micrel Semiconductor, KSZ8862 Datasheet - Page 34

• Manufacturer Part Number: KSZ8862
• Description: 2-port Ethernet Switch With Non-pci Interface And Fiber Support
• Manufacturer: Micrel Semiconductor

Table 2 describes the BIU signal grouping.
Micrel, Inc.
April 2007
Signal
Common Signals
A[15:1]
AEN
BE3N, BE2N,
BE1N, BE0N
D[31:16]
D[15:0]
ADSN
LDEVN
DATACSN
INTRN
Synchronous Transfer Signals
VLBUSN
CYCLEN
SWR
SRDYN
Type
I
I
I
I/O
I/O
I
O
I
O
I
I
I
O
(1)
Function
Address
Address Enable
Address Enable asserted indicates memory address on the bus for DMA access and since
the device is an I/O device, address decoding is only enabled when AEN is low.
Byte Enable
Note 1: BE3N, BE2N, BE1N and BE0N are ignored when DATACSN is low because 32 bit
transfers are assumed.
Note 2: BE2N and BE3N are valid only for the KSZ8862-32 mode, and are NC for the
KSZ8862-16 mode.
Data
For KSZ8862-32 Mode only
Data
For both KSZ8862-32 and KSZ8862-16 Modes
Address Strobe
The rising edge of ADSN is used to latch A[15:1], AEN, BE3N, BE2N, BE1N and BE0N.
Local Device
This signal is a combinatorial decode of AEN and A[15:4], The A[15:4] is used to compare
against the Base Address Register.
Data Register Chip Select (For KSZ8862-32 Mode only)
This signal is used for central decoding architecture (mostly for embedded application).
When asserted, the device’s local decoding logic is ignored and the 32-bit access to QMU
Data Register is assumed.
Interrupt
VLBUSN = 0, VLBus-like cycle.
VLBUSN = 1, burst cycle (both host/system and KSZ8862 can insert wait state)
For VLBus-like access: used to sample SWR when asserted.
For burst access: used to connect to IOWC# bus signal to indicate burst write.
Write/Read
For VLBus-like access: used to indicate write (High) or read (Low) transfer.
For burst access: used to connect to IORC# bus signal to indicate burst read.
Synchronous Ready
For VLBus-like access: exactly the same signal definition of nSRDY in VLBus.
For burst access: insert wait state by the KSZ8862M whenever necessary during the Data
Register access.
BE0N
0
0
1
0
1
1
1
BE1N
0
0
1
1
0
1
1
BE2N
0
1
0
1
1
0
1
34
BE3N
0
1
0
1
1
1
0
Description
32-bit access (32-bit bus only)
Lower 16-bit (D[15:0]) access
Higher 16-bit (D[31:16]) access (32-
bit bus only)
Byte 0 (D[7:0]) access
Byte 1 (D[15:8]) access
Byte 2 (D[23:16]) access (32-bit bus
only)
Byte 3 (D[31:24]) access (32-bit bus
only)
KSZ8862-16/32MQL
M9999-040407-3.0