KSZ8862 Micrel Semiconductor, KSZ8862 Datasheet - Page 36

• Manufacturer Part Number: KSZ8862
• Description: 2-port Ethernet Switch With Non-pci Interface And Fiber Support
• Manufacturer: Micrel Semiconductor

Synchronous Interface
For synchronous transfers, the synchronous dedicated signals CYCLEN, SWR, and RDYRTNN will toggle but the
asynchronous dedicated signals RDN and WRN are de-asserted and stay at the same logic level throughout the entire
synchronous transfer.
The synchronous interface mainly supports two applications, one for VLBus-like and the other for EISA-like (DMA type C)
burst transfers. The VLBus-like interface supports only single-data transfer. The pin option VLBUSN determines if it is a
VLBus-like or EISA-like burst transfer – if VLBUSN = 0, the interface is for VLBus-like transfer; if VLBUSN = 1, the
interface is for EISA-like burst transfer.
Summary
Figure 9 shows the mapping from ISA-like, EISA-like and VLBus-like transactions to the switch’s BIU.
Figure 10 shows the connection for different data bus sizes.
Note: For the 8-bit data bus mode, the internal inverter is enabled and connected between BE0N and BE1N, so even
address will enable the BE0N and odd address will enable the BE1N.
Micrel, Inc.
April 2007
For VLBus-like transfer interface (VLBUSN = 0):
This interface is used in an architecture in which the device’s local decoder is utilized; that is, the BIU decodes latched
A[15:4] and qualifies with AEN (Address Enable) to determine if the switch is the intended target. No burst is
supported in this application. The M/nIO signal connection in VLBus is routed to AEN. The CYCLEN in this application
is used to sample the SWR signal when it is asserted. Usually, CYCLEN is one clock delay of ADSN. There is a
handshaking process to end the cycle of VLBus-like transfers. When the KSZ8862M is ready to finish the cycle, it
asserts SRDYN
the read data. The KSZ8862M holds the read data until RDYRTNN is asserted. The timing waveform is shown in
Figure 22 and Figure 23.
For EISA-like burst transfer interface (VLBUSN = 1):
The SWR is connected to IORC# in EISA to indicate the burst read and CYCLEN is connected to IOWC# in EISA to
indicate the burst write. Note that in this application, both the system/host/memory and KSZ8862M are capable of
inserting wait states. For system/host/memory to insert a wait state, assert the RDYRTNN signal; for the KSZ8862M
to insert the wait state, assert the SRDYN signal. The timing waveform is shown in Figure 20 and Figure 21.
Figure 9. Mapping from ISA-like, EISA-like, and VLBus-like transactions to the KSZ8862M Bus
.
The system/host acknowledges SRDYN by asserting RDYRTNN after the system/host has latched
EISA
VLBus
ISA
Non-burst
Burst
Host Logic
Host Logic
Host Logic
Host Logic
Note: To use DATACSN & 32-bit only for Central decode
36
No Addr Latch
(ADSN = 0)
Address Latch
Central decode
Central decode
(VLBUSN = 1)
Address Latch
KSZ8862M BIU
Local
decode
(VLBUSN = 0)
Local
decode
Asynchronous
Synchronous
Interface
Interface
KSZ8862-16/32MQL
M9999-040407-3.0