MC145152-2 Freescale Semiconductor, Inc, MC145152-2 Datasheet - Page 9

• Manufacturer Part Number: MC145152-2
• Description: Parallel-input Pll Frequency Synthesizer
• Manufacturer: Freescale Semiconductor, Inc

N0 - N9
N Counter Programming Inputs (Pins 11 - 20)
The N inputs provide the data that is preset into the ÷ N counter when it reaches the count of 0. N0 is the
least significant digit and N9 is the most significant. Pull-up resistors ensure that inputs left open remain
at a logic 1 and require only a SPST switch to alter data to the zero state.
A0 - A5
A Counter Programming Inputs
(Pins 23, 21, 22, 24, 25, 10)
The A inputs define the number of clock cycles of f
Section 4.3, “Dual-Modulus
ensure that inputs left open will remain at a logic 1.
OSC
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on-chip reference oscillator when connected to terminals of an external parallel
resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSC
ground and OSC
signal. This signal is typically ac coupled to OSC
levels) dc coupling may also be used. In the external reference mode, no connection is required to OSC
2.2.2
φ
Phase Detector B Outputs (Pins 7, 8)
These phase detector outputs can be combined externally for a loop-error signal.
If the frequency f
φ
If the frequency f
pulsing low. φ
If the frequency of f
minimum time period when both pulse low in phase.
MC
Dual-Modulus Prescale Control Output (Pin 9)
Signal generated by the on-chip control logic circuitry for controlling an external dual-modulus prescaler.
The MC level will be low at the beginning of a count cycle and will remain low until the ÷ A counter has
counted down from its programmed value. At this time, MC goes high and remains high until the ÷ N
counter has counted the rest of the way down from its programmed value (N - A additional counts since
both ÷ N and ÷ A are counting down during the first portion of the cycle). MC is then set back low, the
counters preset to their respective programmed values, and the above sequence repeated. This provides for
a total programmable divide value (N
Freescale Semiconductor
R
V
, φ
pulsing low. φ
in
V
, OSC
Output Pins
out
V
remains essentially high.
out
V
V
R
is less than f
is greater than f
remains essentially high.
to ground. OSC
V
= f
R
and both are in phase, then both φ
Prescaling,”
MC145151-2 and MC145152-2 Technical Data, Rev. 5
R
or if the phase of f
R
in
or if the phase of f
T
may also serve as the input for an externally-generated reference
) = N • P + A where P and P + 1 represent the dual-modulus prescaler
on page
MC145152-2 Parallel-Input (Interfaces with Dual-Modulus Prescalers)
in
21). The A inputs all have internal pull-up resistors that
, but for larger amplitude signals (standard CMOS logic
V
in
is lagging, then error information is provided by φ
that require a logic 0 on the MC output (see
V
is leading, then error information is provided by
V
and φ
R
remain high except for a small
in
to
out
R
9
.